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4. Volume 08

8.1 Registers

A register is a row of D flip-flops sharing one clock: it stores a whole word, and loads a new one at each clock edge. A load-enable input lets it keep its value instead.

One flip-flop stores one bit. Put four side by side, give them the same clock, and they store a 4-bit number - a 4-bit register. At each rising edge, all four capture their D inputs at the same instant.

Loading only when asked

Usually a register should load only sometimes, and hold its value the rest of the time. Put a 2-to-1 multiplexer in front of each flip-flop, choosing between the new data Din and the flip-flop's own output Q. The select input is called LD, for load:

LD·Din + LD'·Q is a 2-to-1 multiplexer choosing Din or Q: True

When LD is 0 the flip-flop reloads its own value, so it holds. When LD is 1 it takes Din. Here is a 4-bit register over five clock edges:

The data on Din changes all the time, but the register only takes it on the edges where LD is 1. The registers inside a processor work exactly like this.

8.2 Shift registers

A shift register passes its bits along one place at every clock edge. It can turn a serial stream - one bit at a time on one wire - into a parallel word, or a word back into a stream.

Chain D flip-flops so that each one's Q drives the next one's D, and give them all the same clock. At every edge, each bit moves one place along, and a new bit enters at the start:

Send the bits of 1101 in, lowest first:

After four edges the whole word sits in the register, ready to be read at once:

after 4 clocks the whole word is in: 4 bits need 4 clocks in, and 4 more to shift out

That is serial-in, parallel-out. Other shift registers load a word in parallel and shift it out one bit at a time, which is how a serial port sends a byte down a single wire.

8.3 Ring and Johnson counters

Feed a shift register's last output back to its input and it counts round a loop of states. A ring counter circulates a single 1. A Johnson counter feeds back the inverse, and gets twice as many states from the same flip-flops.

The ring counter

Load 1000 into a 4-bit shift register and feed Q0 back into Q3. The 1 goes round and round:

ring: 1000 -> 0100 -> 0010 -> 0001 -> 1000

Only one output is 1 at a time, so each output can directly drive one step of a repeating sequence - no decoder needed.

The Johnson counter

Feed back Q0 inverted instead, and the register fills up with 1s, then empties:

Johnson: 0000 -> 1000 -> 1100 -> 1110 -> 1111 -> 0111 -> 0011 -> 0001 -> 0000

with 4 flip-flops: ring counter 4 states, Johnson 8, binary 16

Unused states and lock-up

Four flip-flops have 16 states, and these counters use only some of them. If a counter ever lands in an unused state - at power-up, or after electrical noise - it may never get back:

a ring counter that starts at 0000 stays at 0000 for ever
a Johnson counter started in an unused state: 0101 -> 0010 -> 1001 -> 0100 -> 1010

The ring counter stuck at 0000 has no 1 to pass round. The Johnson counter circles through a second loop of unused states for ever. This trap is called lock-up, and sub-module 8.6 shows how to design it out.

8.4 Ripple counters

In a ripple counter, each flip-flop is clocked by the one before. It needs no gates at all, but the change ripples through the stages one after another, and on the way the outputs pass through wrong values.

A T flip-flop with T = 1 halves its clock (Volume 07). Chain four of them, each clocked by the inverted output of the one before. Then bit 1 toggles every time bit 0 falls, bit 2 every time bit 1 falls, and so on. That is exactly binary counting:

Watching it ripple

The simulator built this counter from the gate-level flip-flops of Volume 07 and ran it for 18 clock cycles. Here is every value the outputs passed through:

values the outputs pass through: 0 1 0 2 3 2 0 4 5 4 6 7 6 4 0 8 9 8 10 11 10 8 12 13 12 14 15 14 12 8 0 1 0 2

It does count 0, 1, 2, 3 and on up to 15 - but between the counts it visits wrong values. Going from 7 to 8, the change ripples through every stage:

after the edge at step 300 (from 7 to 8): 7 -> 6 -> 4 -> 0 -> 8
after that edge Q0, Q1, Q2, Q3 settle 3, 5, 7, 8 steps later

The delay grows with every stage, so a long ripple counter can only run slowly. And anything that reads its outputs without waiting may see 6, 4 or 0 on the way from 7 to 8.

8.5 Synchronous counters

In a synchronous counter every flip-flop shares one clock, and gates decide which ones toggle. All the bits change together, at one clock-to-Q delay after the edge.

Look at binary counting again: a bit toggles when every bit below it is 1. So with T flip-flops on a common clock, each T input is the AND of the bits below:

T0 = 1, T1 = Q0, T2 = Q0·Q1, T3 = Q0·Q1·Q2

The simulator built this one from the same gate-level flip-flops, with a gate-level AND chain, and ran the same 18 cycles:

values the outputs pass through: 0 1 3 2 3 7 4 5 7 6 7 15 8 9 11 10 11 15 12 13 15 14 15 0 1 3 2
after the edge from 7 to 8: 7 -> 15 -> 8
after that edge Q0, Q1, Q2, Q3 settle 3, 3, 3, 2 steps later

Every bit now settles within one step of the others, instead of spreading over five steps. But look closely: the outputs still show one wrong value between counts, such as 15 on the way from 7 to 8. It lasts a single step, and it comes from the flip-flop itself: in Volume 07's measurement, Q rises 2 steps after the edge but falls 3 steps after it. So the rising bit arrives one step before the falling ones.

8.6 A counter for any sequence

A counter can follow any sequence you choose. Write down each state and its next state, look up the flip-flop inputs in the excitation table, then simplify each input with a K-map. Finally, check where the unused states go.

Say a counter must run 000, 001, 011, 111, 110, 100 and back to 000, using JK flip-flops.

Step 1: the state table with its excitations

For each state, write the next state, then use the JK excitation table from Volume 07 for each bit:

Step 2: simplify each input

The two states the sequence never uses, 010 and 101, are don't cares. With them, each input's K-map simplifies to a single letter:

J2 = Q1
K2 = Q1'
J1 = Q0
K1 = Q0'
J0 = Q2'
K0 = Q2

from 000: 000 -> 001 -> 011 -> 111 -> 110 -> 100 -> 000

Step 3: check the unused states

This step is the one that is easy to forget. Treating 010 and 101 as don't cares let the K-maps choose their next states freely - and they chose badly:

from unused 010: 010 -> 101 -> 010 -> 101 -> 010
from unused 101: 101 -> 010 -> 101 -> 010 -> 101
the unused states only lead to each other (lock-up): True

Step 4: design the lock-up out

The fix is to stop treating the unused states as don't cares, and give each one a next state that joins the sequence. Sending both to 000 costs a few more gates:

J2 = Q1·Q0
K2 = Q1'
J1 = Q2'·Q0
K1 = Q0'
J0 = Q2'·Q1'
K0 = Q2
from unused 010: 010 -> 000 -> 001
from unused 101: 101 -> 000 -> 001
every unused state now joins the sequence on the next clock: True

What you learned

• A register is D flip-flops on one clock; a multiplexer on each input gives it a load enable.
• A shift register moves its bits one place per clock, turning serial data into parallel and back.
• A ring counter circulates one 1 through n states; a Johnson counter uses 2n states from n flip-flops.
• Counters that skip states can lock up in the unused ones.
• A ripple counter clocks each stage from the last. Its delay grows with every stage, and it passes through wrong values.
• A synchronous counter clocks every stage together, with T inputs from ANDs of the bits below. Its bits settle within one step of each other.
• To design a counter for any sequence: state table, excitation table, K-maps - then check every unused state.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Register
• Shift register
• Ring counter
• Johnson counter
• Lock-up
• Ripple counter
• Synchronous counter

Practice

Interview corner

Volume 09 moves out to real chips: memories, converters between analogue and digital, and the logic families that gates are built from.