From Transistor to Logic Gate (CMOS)
Every logic gate in every chip is a handful of transistors. This volume builds them: NMOS and PMOS switches, the CMOS inverter that pairs them so no current flows at rest, and the NAND and NOR gates whose truth tables fall straight out of their switches. It shows where a chip's power really goes, and what the voltage levels on a datasheet mean when two chips are joined.
- How NMOS and PMOS transistors switch, and why each is good at one job
- How a CMOS inverter works, and why its steep curve makes logic robust
- How CMOS NAND and NOR gates are built from series and parallel transistors
- Why a CMOS chip uses power only when it switches, and why lower voltages save so much
- What VOH, VOL, VIH and VIL mean, and how to check two chips can talk
- Volume 05: the MOSFET as a switch. Knowing what NAND and NOR gates do helps; Digital Logic from Zero, Volume 02 covers them.
6.1 NMOS and PMOS as switches
Inside a chip, every transistor is a MOSFET used as a switch. An NMOS transistor turns on when its gate is high, and is good at pulling an output down to 0. A PMOS transistor turns on when its gate is low, and is good at pulling an output up to 1.
Two kinds of switch
Volume 05 used an N-channel MOSFET to switch a lamp. Chips use the same device, far smaller, and its partner, the P-channel MOSFET. Written short, they are NMOS and PMOS:
| Transistor | Turns on when its gate is | Its source goes to | Good at pulling the output |
|---|---|---|---|
| NMOS | high (1) | ground | down, to 0 |
| PMOS | low (0) | the supply | up, to 1 |
A PMOS is drawn with a small circle on its gate, a reminder that it works the opposite way round. In these drawings, VDD marks the supply rail - the 3.3 V that feeds the chip - and each input is a small open circle with its letter.
circuit two-switches: A = 3.3 V: N1 on, Y1 = 32.7 mV; B = 3.3 V: P1 off, Y2 = 0 V
circuit two-switches: A = 0 V: N1 off, Y1 = 3.3 V; B = 0 V: P1 on, Y2 = 3.27 V
Each switch works, and each one inverts: a high gate on N1 gives a low Y1. But the resistors cause trouble. While N1 is on, current flows through R1 all the time:
while N1 pulls Y1 down, R1 wastes 327 µA
That is tiny for one gate. A chip has millions of gates, and together they would waste watts doing nothing.
Why each kind has its job
An NMOS conducts only while its gate is at least its threshold voltage above its source. Ask it to pull an output up, and the output is its source: as the output rises, the gate's lead over it shrinks, until the transistor turns itself off:
an NMOS with its gate at 3.3 V, passing 3.3 V to a 1 MΩ load, only gets it to 2.45 V
an NMOS can never pass more than 3.3 V - 0.7 V = 2.6 V
So an NMOS passes a clean 0 but a weak 1. A PMOS is the mirror image: it passes a clean 1 but a weak 0. CMOS puts each one where it is strong.
Which transistor turns on when its gate is at 0 V, with its source at the 3.3 V supply?
Show the answer
Answer: C. A PMOS turns on when its gate is well below its source. With the source at 3.3 V and the gate at 0 V, it is fully on. An NMOS needs its gate above its source.
6.2 The CMOS inverter
A CMOS inverter is one PMOS above one NMOS, with their gates joined. Whatever the input, one is on and the other is off, so the output is joined firmly to the supply or to ground. Once it has settled, no current flows through the gate.
The inverter
circuit inverter: A = 0 V: P1 on, N1 off, Y = 3.3 V; the supply gives 0 A
circuit inverter: A = 3.3 V: P1 off, N1 on, Y = 0 V; the supply gives 0 A
The resistors are gone. In their place, each transistor pulls one way, and the other is always off. So the output reaches the full 3.3 V or the full 0 V, and in either state the supply gives no current at all.
Between 0 and 1
What does the inverter do with an input halfway? The on-off switch model is too rough for this, so the course uses a finer model of each transistor, in which its current grows smoothly with its gate voltage:
the switching point, where Y = A: 1.65 V
Y falls from 3 V to 0.3 V while A rises only from 1.40 V to 1.90 V
A small change in the input makes a big change in the output. That is what makes digital logic robust: a slightly wrong input voltage still gives a nearly perfect output, so errors are cleaned up at every gate instead of piling up.
A CMOS gate has a PMOS network pulling up and an NMOS network pulling down. For every input, exactly one of them conducts.
In a CMOS inverter with its input at 3.3 V, which transistor is on?
Show the answer
Answer: B. A high input turns the NMOS on, joining Y to ground, and turns the PMOS off. The output is 0.
6.3 CMOS NAND and NOR
A NAND gate is two PMOS in parallel above two NMOS in series. A NOR gate turns that round: two PMOS in series above two NMOS in parallel. Series means both must be on; parallel means either will do.
The NAND gate
The pull-down is two NMOS in series, so Y is pulled down only when A and B are both 1. The pull-up is two PMOS in parallel, so Y is pulled up when either input is 0. The drawing shows both inputs high:
circuit nand: drawn with A = 3.3 V and B = 3.3 V: Y = 0 V, and the supply gives 0 A
To get the truth table, each transistor is treated as a switch - on or off, according to its input. The switches were read from the drawing, and then tried with all four input patterns:
nand pull-up (PMOS): A joins out to vdd; B joins out to vdd
nand pull-down (NMOS): A joins out to x; B joins x to gnd
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
nand: in every row exactly one network conducts: True
The NOR gate
circuit nor: drawn with A = 0 V and B = 0 V: Y = 3.3 V, and the supply gives 0 A
nor pull-up (PMOS): A joins m to vdd; B joins out to m
nor pull-down (NMOS): A joins out to gnd; B joins out to gnd
nor: in every row exactly one network conducts: True
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
The pattern
The two networks are mirror images. Where the NMOS network is in series, the PMOS network is in parallel, and the other way round. That guarantees one of them conducts and the other does not, for every input. It also explains why chips are built from NAND and NOR rather than AND and OR: each one costs just four transistors, and it inverts naturally. An AND gate is a NAND followed by an inverter:
a 2-input NAND or NOR: 4 transistors; an inverter: 2
Digital Logic from Zero, Volume 02 shows how every other gate can be built from NANDs alone.
In a CMOS NOR gate, how are the two NMOS transistors connected?
Show the answer
Answer: D. NOR is 0 when either input is 1. So the pull-down must conduct if either NMOS is on: they are in parallel between Y and ground.
6.4 Why CMOS uses so little power
A settled CMOS gate draws no current, because its pull-up and pull-down are never on together. It uses energy only when it switches, charging and emptying the capacitance it drives - so power grows with the square of the supply voltage.
No current at rest
Module 2 showed the settled inverter drawing 0 A in both states. That is the great gift of CMOS: a chip full of gates that are not switching uses almost no power. The resistor switches of Module 1 wasted current in every gate whose output was low.
A brief current while switching
As the input passes through the middle, both transistors are partly on for a moment, and a little current flows straight through:
the largest supply current, at the switching point: 105 µA
A fast edge passes through the middle in a moment, so this costs very little. A slow edge lingers there, wasting current - one more reason, after Volume 03's Schmitt trigger, to keep edges fast.
The real cost: charging capacitance
Every output drives wires and the gates of other transistors, and all of them have capacitance. Each time the output rises, the supply charges that capacitance; each time it falls, the charge is dumped to ground. One full cycle of charging and emptying takes energy from the supply:
energy per charge and discharge = C x V x V
10 pF switched at 3.3 V: 109 pJ each cycle; at 10 MHz that is 1.09 mW
10 pF switched at 1.65 V: 27.2 pJ each cycle; at 10 MHz that is 272 µW
10 pF switched at 0.8 V: 6.4 pJ each cycle; at 10 MHz that is 64 µW
Halve the voltage, and the power falls to a quarter. That is why chips have moved from 5 V to 3.3 V, and their insides to under 1 V. For a whole chip:
power = activity x C x V x V x frequency
a chip with 1 nF of wiring and gates, a tenth of it switching each cycle, at 0.8 V and 1 GHz: 64 mW
Here activity is the share of the capacitance that switches each cycle.
Leakage
Real transistors that are off still leak a tiny current. In one gate it is almost nothing. Across the billions of transistors in a modern processor, it adds up to a real share of the power, even when the chip is doing nothing. Designers fight it by switching whole blocks off.
A chip's supply voltage is reduced from 3.3 V to 1.65 V, with everything else the same. What happens to its switching power?
Show the answer
Answer: A. Switching power grows with V × V. Halving V divides the power by 2 × 2 = 4: from 1.09 mW to 272 µW in the example.
6.5 Logic levels and thresholds
A chip promises how high its 1s and how low its 0s will be, and it states what it will accept as a 1 or a 0. The gaps between the two are the noise margins. Two chips work together only if one's outputs meet the other's inputs.
Four voltages
Every logic family's datasheet gives four numbers:
- VOH: the lowest voltage its outputs give for a 1.
- VOL: the highest voltage its outputs give for a 0.
- VIH: the lowest voltage its inputs are sure to read as 1.
- VIL: the highest voltage its inputs are sure to read as 0.
Between VIL and VIH lies a no-man's-land, where an input might read either way. Outputs must never stop there.
| Family | VOH | VOL | VIH | VIL | NMH | NML |
|---|---|---|---|---|---|---|
| 3.3 V CMOS (LVTTL levels) | 2.4 | 0.4 | 2.0 | 0.8 | 0.4 | 0.4 |
| 5 V CMOS (example) | 4.9 | 0.1 | 3.5 | 1.5 | 1.4 | 1.4 |
| Standard TTL | 2.4 | 0.4 | 2.0 | 0.8 | 0.4 | 0.4 |
NMH = VOH - VIH; NML = VIL - VOL
The noise margin is how much noise a signal can pick up on its way from one chip to the next and still be read correctly. The figures above are typical; always take real values from the datasheet of the part you use.
Mixing 3.3 V and 5 V chips
3.3 V output into a 5 V CMOS input: VOH 2.4 V is below VIH 3.5 V, so a 1 is not guaranteed
3.3 V output into a TTL input: VOH 2.4 V clears VIH 2.0 V by 400 mV
5 V output into a 3.3 V input: divide it: 5 V x 3.3 kΩ / (1.8 kΩ + 3.3 kΩ) = 3.24 V
A 5 V output can also harm a 3.3 V input, unless the datasheet says the input is 5 V tolerant. The voltage divider from Volume 02 fixes that for slow signals. Fast ones use a small level-shifter chip.
A family has VOH = 2.4 V and VIH = 2.0 V. What is its high noise margin?
Show the answer
Answer: C. NMH = VOH - VIH = 2.4 V - 2.0 V = 0.4 V. A 1 can pick up 0.4 V of noise and still be read as a 1.
What you learned
- An NMOS turns on with a high gate and passes a clean 0; a PMOS turns on with a low gate and passes a clean 1.
- A CMOS inverter is a PMOS above an NMOS; one is always off, so the output reaches the rails and no current flows at rest.
- Its output falls steeply around the switching point, so every gate cleans up slightly wrong inputs.
- NAND is PMOS in parallel above NMOS in series; NOR is the mirror image. Each takes four transistors.
- CMOS power comes from switching: C × V × V per cycle, so lower voltages save power fast.
- VOH, VOL, VIH and VIL set the noise margins; a 3.3 V output cannot be trusted to drive a 5 V CMOS input.
Key words from this volume
Every word below has a plain-English entry in the glossary.
Practice
Switching energy
10 pF is switched at 10 MHz. How much power does it take at 5 V, and at 1.8 V?
Show the solution
10 pF switched at 5 V: 250 pJ each cycle; at 10 MHz that is 2.5 mW
10 pF switched at 1.8 V: 32.4 pJ each cycle; at 10 MHz that is 324 µW
Noise margins
A family has VOH 2.9 V, VOL 0.3 V, VIH 2.1 V and VIL 0.9 V. What are its noise margins?
Show the solution
a family with VOH 2.9 V, VOL 0.3 V, VIH 2.1 V and VIL 0.9 V: NMH = 800 mV, NML = 600 mV
Design a gate
Using the NAND and NOR pattern, describe the transistors of a CMOS gate for Y = (A·B·C)' - a three-input NAND.
Show the solution
Three NMOS in series from Y to ground, so Y is pulled down only when all three inputs are 1. Three PMOS in parallel from the supply to Y, so Y is pulled up when any input is 0. Six transistors in all.
Interview corner
Why CMOS
"Why does CMOS draw almost no static power, and where does its power go?"
Show the solution
"In a static CMOS gate, the PMOS pull-up and NMOS pull-down networks are complementary. For any settled input, exactly one conducts, so there is no path from supply to ground and no current at rest. Power goes in three places. Mostly, it's switching - charging and discharging the load capacitance, C V squared per cycle times the frequency and the activity. A little is short-circuit current while an input passes through the middle and both networks conduct briefly. And in modern processes, leakage through transistors that are meant to be off adds a static share."
Volume 07 turns to the supply itself: batteries, regulators and the capacitors that keep a chip's supply steady.