Maximum clock frequency from propagation, logic and setup time
BlinkNBuild practice problem · GATE standard, authored and verified in-house
In the synchronous circuit below, data launched by flip-flop FF1 propagates through a block of combinational logic and is captured by FF2 on the next rising edge of the same clock.
- Clock-to-Q propagation delay, $t_{cq} = 2\ \text{ns}$
- Worst-case combinational delay, $t_{logic} = 6\ \text{ns}$
- Setup time, $t_{su} = 1\ \text{ns}$
- Clock skew between FF1 and FF2 is zero
The maximum clock frequency, in MHz, is ________.
Show the step-by-step derivation
Answer
111.11 MHz (accept 111 to 111.2) MHz (accept 111 to 111.2)
Step-by-step derivation
- Data is launched by the rising edge at $t = 0$ and must be stable at FF2's D input a setup time before the next rising edge at $t = T$. The setup constraint is therefore $$t_{cq} + t_{logic} + t_{su} \le T.$$
- With zero skew there is no correction term, so substituting directly: $$2 + 6 + 1 = 9\ \text{ns} \le T.$$
- The minimum legal period is $T_{min} = 9\ \text{ns}$, and the maximum frequency is its reciprocal: $$f_{max} = \frac{1}{T_{min}} = \frac{1}{9 \times 10^{-9}\ \text{s}}.$$
- Evaluating: $$f_{max} = 1.1111 \times 10^{8}\ \text{Hz} = \mathbf{111.11\ MHz}.$$
- Sanity check on the units: nanoseconds and megahertz are reciprocal at $1\ \text{ns} \leftrightarrow 1000\ \text{MHz}$, so $9\ \text{ns}$ must give $1000/9 = 111.1\ \text{MHz}$. ✓
The trap this question is built around
Hold time never appears in the maximum-frequency equation. Hold is a constraint between the same pair of edges, so it is independent of the period - a design that fails hold fails at every frequency, including DC. Adding $t_h$ to the sum is the most common way to lose this mark.