Transistor count for a static CMOS AND-OR-INVERT gate
BlinkNBuild practice problem · GATE standard, authored and verified in-house
The function $Y = \overline{(A \cdot B) + C}$ is implemented as a single complex gate in static CMOS. The total number of transistors required is ________.
Show the step-by-step derivation
Answer
6 transistors transistors
Step-by-step derivation
- A static CMOS gate has two networks: a pull-down network (PDN) of NMOS devices that connects the output to ground when the function is $0$, and a pull-up network (PUN) of PMOS devices that connects it to $V_{DD}$ when the function is $1$. The two are duals of each other.
- Pull-down network. $Y$ goes low exactly when $(A \cdot B) + C = 1$. In an NMOS network, AND becomes a series connection and OR becomes a parallel connection. So the PDN is ($A$ in series with $B$) in parallel with $C$: three NMOS transistors.
- Pull-up network. The PUN is the dual: series becomes parallel and parallel becomes series. So it is ($A$ in parallel with $B$) in series with $C$: three PMOS transistors.
- Total transistor count: $$N = N_{PDN} + N_{PUN} = 3 + 3 = \mathbf{6}.$$
- General rule: a static CMOS complex gate needs exactly $2n$ transistors for $n$ inputs, one NMOS and one PMOS per input. Here $n = 3$ inputs $\Rightarrow 6$ transistors - which is why AOI and OAI gates are so cheap, and why synthesis tools reach for them constantly.
The trap this question is built around
Building this from discrete gates instead. An AND (6 T) plus a NOR (4 T) is 10 transistors and two gate delays. The single complex gate is 6 transistors and one gate delay, because the inversion is free - static CMOS is naturally inverting, so the bubble at the output costs nothing.