1. Home
2. Academy
3. Digital Logic from Zero
4. Volume 07

7.1 Why circuits need memory

Every circuit so far forgets: its output depends only on its inputs right now. To remember, a circuit needs feedback - a loop that feeds its output back to its own input. The simplest memory is two NOT gates in a ring.

A calculator must remember the first number while you type the second. A counter must remember where it has got to. A lock must remember which digits you have already pressed. None of these can be built from the circuits of Volumes 02 to 06, whose outputs depend only on their inputs at that moment. They need sequential logic: circuits whose output also depends on what happened before.

Two NOT gates in a ring

Join two NOT gates in a loop, as in Figure 7.1. If the first output is 0, the second is 1, which keeps the first at 0. If the first is 1, the second is 0, which keeps the first at 1. Either way, the loop holds itself steady.

figure ring: holds 0 for ever if it starts at 0, and 1 if it starts at 1: True

A circuit with two steady states like this is bistable. The trouble is that nothing can change it: there is no input. The rest of this volume adds inputs.

7.2 The SR latch

Replace the NOT gates with NOR gates and the ring gets two inputs. The SR latch sets its output to 1 when S is 1, resets it to 0 when R is 1, and remembers when both are 0.

A NOR gate's output is 0 whenever any input is 1. So R = 1 forces Q to 0, and S = 1 forces Q' to 0, which then makes Q equal 1. With S and R both 0, each gate simply inverts the other's output, and the latch holds whatever it had.

figure sr-nor: unknown until set, then set, holds, resets, holds and sets as its table says: True

Notice the start. Before S is first raised, nobody knows what Q holds - the simulator shows it as unknown. A real latch powers up in either state. That is why real designs reset their memories before use.

The SR latch's table

Why is S = R = 1 not allowed? Both NOR gates are then forced to 0, so Q and Q' are both 0 - no longer opposites:

with S = R = 1, Q and Q' are both 0: True

Worse is what happens when both inputs drop to 0 at the same moment. Each gate sees two 0s and heads for 1, then each sees the other's 1 and heads back to 0. With two perfectly equal gates, the latch oscillates:

In a real circuit the two gates are never exactly equal, so the latch soon falls one way or the other. But which way, and when, cannot be predicted. So the rule is simple: never set S and R to 1 together.

7.3 The D latch

A D latch has a data input D and an enable EN. While EN is 1 the latch is transparent: Q follows D. When EN goes to 0, the latch holds whatever D was at that moment.

The SR latch has two awkward points: two inputs to manage, and a combination that is not allowed. The D latch solves both. It makes S and R from a single input, D, so they can never both be 1, and it adds an enable that decides when D may get through.

Q rises 2 steps after D rises, and falls 4 steps after D falls (the falling path has the NOT gate)
figure d-latch: settles to D within 4 steps while EN = 1, and holds while EN = 0: True

The first line is a reminder that real paths have different lengths. Q rises in two steps but falls in four, because the falling change has to pass through the extra NOT gate first.

7.4 The D flip-flop

A D flip-flop copies D to Q only at the rising edge of its clock, and holds it until the next rising edge. It is built from two D latches, a master and a slave, that are never open at the same time.

Master and slave

The master latch is open while the clock is 0, and the slave while the clock is 1. So while the clock is low, the master follows D and the slave holds. The moment the clock rises, the master closes on the value D had, and the slave opens to pass that value to Q. Nothing D does after that can get past the closed master until the clock falls and rises again.

Figure 7.8 shows a gate-level flip-flop built this way, from two NAND latches like the one in sub-module 7.3 and a NOT gate on the clock. Every gate takes one step:

rising edges at 4, 12, 20, 28, 36, 44; Q changes at 14, 23, 38
every change of Q comes just after a rising edge: True
D pulses high from 21 to 23, while CLK is high and the master is shut, and Q never sees it: True

A circuit that acts only at the edge of a clock is edge-triggered. This is what makes large digital systems work. Every flip-flop in a chip changes at the same instant, the rising edge, and between edges the logic has a whole clock period to settle.

7.5 JK and T flip-flops

Other flip-flops decide their next state differently. A JK flip-flop can hold, reset, set or toggle. A T flip-flop toggles when T is 1. Each is summed up by a characteristic equation, and each has an excitation table for designing with it.

The JK flip-flop

The JK flip-flop fixes the SR latch's forbidden input. J acts like set and K like reset, but J = K = 1 is allowed: it toggles Q to the opposite value.

Its characteristic equation - the characteristic table written as a formula - gives the next state in one line:

Q next = J·Q' + K'·Q gives hold, reset, set, toggle for JK = 00, 01, 10, 11: True

The T flip-flop

A T flip-flop has one input. When T is 0 it holds, and when T is 1 it toggles. Its equation is Q next = T ⊕ Q:

With T held at 1, Q toggles on every rising edge. Its output is a clock at half the speed - the start of every counter in Volume 08:

Excitation tables

A characteristic table answers "given the inputs, what comes next?". When designing, the question is the other way round: "to get from this Q to that Q, what inputs do I need?". That is an excitation table. X means the input may be 0 or 1:

Read the JK row for 0 to 1: J must be 1, but K does not matter. J = 1 with K = 0 sets Q, and J = 1 with K = 1 toggles it - and both take a 0 to a 1. Those X entries are don't cares, and Volume 08 uses them to make counters smaller.

7.6 Setup, hold and clock-to-Q

A flip-flop needs D to be steady for a short setup time before the clock edge and a short hold time after it. Its output then changes one clock-to-Q delay after the edge. All three come from the delays of the gates inside.

A flip-flop cannot capture D in zero time. Inside, the master latch has to settle on the new value before it shuts. If D changes too close to the edge, the flip-flop may catch the old value, the new one, or something in between.

Measuring them on the simulated flip-flop

The simulator can find these numbers for the gate-level flip-flop of sub-module 7.4. It changed D at different times around a clock edge, once rising and once falling, and watched Q. A capture is clean when Q changes exactly as it does for a D that changed long before: once, to the right value, at the usual time. After the edge, clean means Q does not move at all.

setup: D must be steady at least 3 steps before the edge
hold: D may change from 1 step after the edge
clock-to-Q: Q rises 2 steps after the rising edge, and falls 3 steps after it

So this flip-flop's setup time is 3 gate delays and its hold time is 1. Notice that a falling D needs more time than a rising one, because it passes through the extra NOT gate. Datasheets quote the worst case, and so should you.

What goes wrong in a real chip

In the simulator, a late change gives a late or glitching output. In a real flip-flop it can be worse. If D changes right at the edge, the latch inside can be caught exactly between 0 and 1, like a coin balanced on its edge. It stays there for an unpredictable time before falling one way or the other. This is metastability, and a simulation that only knows 0 and 1 cannot show it.

The cure is to keep the rules: D steady for the setup time before every edge, and for the hold time after it. The course on static timing analysis is about checking exactly that, for every flip-flop in a chip.

What you learned

• Memory needs feedback: two NOT gates in a ring hold one bit for ever.
• An SR latch sets with S, resets with R and holds with both at 0; S = R = 1 is not allowed.
• A D latch is transparent while EN is 1 and holds while EN is 0. It is level sensitive.
• A D flip-flop is two latches, master and slave, so Q changes only at the rising clock edge.
• A JK flip-flop holds, resets, sets or toggles; a T flip-flop toggles when T = 1: Q next = T ⊕ Q.
• An excitation table gives the inputs needed for each change of Q, with don't cares.
• Setup and hold times keep D steady around the edge, and clock-to-Q is the delay to the output. The simulated flip-flop needed 3 and 1 gate delays, and its output followed in 2 or 3.
• Breaking setup or hold in a real chip can cause metastability.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Feedback
• Sequential logic
• Bistable
• SR latch
• Unknown value (X)
• D latch
• Level-sensitive
• D flip-flop
• Edge-triggered
• JK flip-flop
• T flip-flop
• Characteristic table
• Excitation table
• Setup time
• Hold time
• Clock-to-Q delay
• Metastability

Practice

Interview corner

Volume 08 puts flip-flops to work: registers that store words, shift registers and counters.