Static Timing Analysis from Zero: Setup, Hold and Every Clocking Case
Static timing analysis is how a chip is proved fast enough before anyone builds it. It is arithmetic, not magic: data leaves one flip-flop, takes time to travel, and has to arrive before the next clock edge. This course starts from zero - no prior electronics assumed - and works every check by hand, one number at a time, until a real timing report reads like a sentence.
Start here
Start with Volume 00. It takes about forty minutes and teaches the four ideas the rest of the course stands on: what a clock is, what a flip-flop does with it, why nothing in a chip is instant, and how to read a timing diagram. Then take the volumes in order - each one uses only what came before it.
Every number in this course was computed before it was written down, by a small timing model kept beside the lessons. So when a page says the slack is 0.42 ns, that is a result, not a guess. Each new word is underlined with dots - point at it (or tap it) to see what it means, and every sub-module ends with a quick check.
Volume 07 of the Verilog course is the fast version of setup, hold and f_max for engineers who already write RTL. This course is the slow one: it assumes nothing, works every example numerically, and then goes much further - every clocking case, latches, I/O timing, variation, crosstalk, the full SDC language and a worked timing closure. Read that volume in an hour; use this course to actually learn it.
Timing analysis is the same arithmetic on an FPGA and on an ASIC. When you want the tool-specific half, FPGA Mastery Volume 03 covers XDC constraints and I/O budgeting in Vivado, and ASIC Volume 06 covers multi-corner sign-off with OpenSTA. Both assume the ideas taught here.
Full syllabus
Part I - What timing analysis is
- 00 Start Here: Clocks, Delay and Units How the course works, then the four ideas it stands on: what a clock and a flip-flop do, why nothing is instant, how to read a timing diagram, and the units - ns, ps, MHz and GHz. Live
- 01 Why Chips Need Timing Analysis The race between data and clock, the two checks that decide whether a chip works - setup and hold - what a failure looks like on real silicon, and why simulation cannot find these bugs. Live
- 02 Where Delay Comes From Gate delay and the four things that change it, wire delay as resistance and capacitance, what slew is and why it spreads, library delay tables made simple, and the three numbers every flip-flop has. Live
- 03 Timing Paths Start points and end points, the four path types every tool groups its checks into, launch and capture edges, timing arcs and unateness, and why the clock path is analysed separately from the data path. Live
Part II - The two checks, worked by hand
- 04 Setup Analysis, Step by Step Arrival time, required time and setup slack built up one term at a time, ten worked problems, the maximum frequency a path allows, and a real setup report read line by line. Live
- 05 Hold Analysis, Step by Step The hold check from first principles, why the clock period is missing from it, why that makes a hold violation scrap rather than a slower part, ten worked problems and a hold report read line by line. Live
Part III - The clock, in detail
- 06 The Clock in Detail Period, duty cycle and waveform; source and network latency; skew as the difference that helps setup and hurts hold; jitter and uncertainty; and the difference between an ideal and a propagated clock. Live
- 07 Every Clocking Case Half-cycle paths, inverted and negative-edge clocks, generated and divided clocks, related clocks with awkward ratios, asynchronous clocks and clock groups, clock muxes and clock-gating checks - each worked numerically. Live
Part IV - Telling the tool the truth
- 08 Timing Exceptions False paths, multicycle paths on one clock and between two, the hold check that a setup multicycle drags with it, max and min delay, case analysis and disabled arcs - and the damage each does when it is wrong. Live
- 09 Latches and Time Borrowing How a latch differs from a flip-flop, latch setup and hold, time borrowing worked cycle by cycle, latch-based pipelines, and pulsed latches in brief. Live
- 10 Input and Output Timing Constraining the world outside the chip: input delay and output delay from a datasheet, virtual clocks, system-synchronous versus source-synchronous interfaces, and DDR timing. Live
Part V - Reality: variation and noise
- 11 Variation: Corners and OCV Why one chip is not another: PVT corners, RC corners, on-chip variation and derating, AOCV and POCV in plain words, and the clock reconvergence pessimism a tool gives back. Live
- 12 Signal Integrity Crosstalk in timing terms: aggressors and victims, the delta delay a switching neighbour adds or removes, glitches that look like data, and the ways each is fixed. Live
Part VI - Constraints, closure and revision
- 13 SDC Constraints, Complete The constraint language line by line: defining clocks and their properties, I/O constraints, exceptions, design rules for transition, capacitance and fanout, and how to check that the constraints say what you meant. Live
- 14 Timing Closure What to do when the slack is negative: fixing setup, fixing hold, engineering change orders, how closure differs on an FPGA and an ASIC, and one design closed from first report to last. Live
- 15 STA Problem Vault and Revision One-page formula sheet, forty numerical problems solved in full, twenty concept questions asked the way interviewers ask them, report-reading drills and flashcards. Live
What you need before starting
| What | Why | Free option |
|---|---|---|
| Nothing but curiosity | Volume 00 teaches every idea the course needs | - |
| A calculator | Timing is arithmetic, and you will do a lot of it | The one on your phone |
| Optional: a timing tool to play with | To see real reports | OpenSTA and OpenROAD, both free and open source |
| Optional: Vivado or Quartus | To constrain a real FPGA design | Both have free editions |