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4. Volume 08

8.1 False paths

A false path is a path the tool is told never to time, because it can never carry data that matters. Used correctly it removes violations that do not exist. Used wrongly it hides one that does.

A timing tool times every path it can find, including paths that the design can never actually use. When one of those fails, it fills the report with a violation nobody needs to fix. A timing exception tells the tool the truth about such a path.

A path that cannot happen

Two multiplexers share one select line, S. When S is 0, both pass their first input; when S is 1, both pass their second. At 10 ns, with 0.25 ns clock-to-Q and 0.10 ns setup:

The tool does not know that S cannot be two values at once. So it reports -1.75 ns as the worst path. The real worst path is 0.45 ns, and it passes.

set_false_path -through [get_pins u_mux1/I0] -through [get_pins u_mux2/I1]

A path that does not need timing

A configuration register is written once at power-on, while the logic it controls is idle. Its path through a multiplier takes 12.30 ns on a 10 ns clock, so the tool reports -2.65 ns. But by the time anything reads the result, the register has been steady for thousands of cycles.

That can also be a false path - but only if the design really guarantees it. If software could ever write that register while the logic runs, the path is real, and the violation is a bug.

8.2 Multicycle paths on one clock

A multicycle path is given more than one clock cycle for setup, because the design only uses its result every few cycles. Relaxing setup drags the hold check along with it, and that must be put back by hand.

Some logic is too slow for one cycle, and the design knows it. A slow calculation is started, and its result is only read three cycles later. An enable signal makes both registers act only every third edge.

Take such a path at 10 ns: clock-to-Q 0.30 ns (0.20 fastest), logic 24.50 ns (1.10 fastest), setup 0.10 ns and hold 0.05 ns.

The hold trap

Look at the middle row. The setup exception moved the capture edge from 10 to 30. The default hold check is always one capture edge before the setup capture - so it moved too, from 0 to 20.

Now hold wants the data to arrive no earlier than 20.05 ns. It arrives at 1.30 ns. The hold check says -18.75 ns: a violation that is pure fiction, and that the tools would try to "fix" with about 19 ns of delay cells.

set_multicycle_path 3 -setup -from [get_cells u_src] -to [get_cells u_dst]
set_multicycle_path 2 -hold  -from [get_cells u_src] -to [get_cells u_dst]

8.3 Multicycle paths between two clocks

When a multicycle path crosses between two clocks, you must say whose cycles you are counting. The option -end counts the capture clock and moves the capture edge. The option -start counts the launch clock and moves the launch edge.

Take a path between a 10 ns clock and a 5 ns clock. It has clock-to-Q 0.20 ns and logic 8.20 ns (0.80 fastest), with setup 0.10 ns and hold 0.05 ns. Without an exception, either direction gets one fast period: 5 ns. The design gives it two.

Slow to fast: count the fast capture clock, with -end

Fast to slow: count the fast launch clock, with -start

The pattern is the same as on one clock: an N-cycle setup exception needs an (N-1)-cycle hold exception, counted in the same clock.

set_multicycle_path 2 -setup -start -from [get_clocks fast] -to [get_clocks slow]
set_multicycle_path 1 -hold  -start -from [get_clocks fast] -to [get_clocks slow]

Counting the wrong clock

Put -end on the fast-to-slow path by mistake. The tool moves the capture edge by one slow period, from 10 to 20 ns. The path now gets 15 ns instead of 10, and shows 6.50 ns of slack it does not have.

8.4 Max delay and min delay

set_max_delay and set_min_delay replace the clock relationship with a plain number. Their main use is on crossings between unrelated clocks, where there is no clock relationship to use.

Volume 07 put unrelated clocks in separate clock groups, which stops all timing between them. But some crossings still need a bound. The classic one is a Gray-coded pointer in an asynchronous FIFO. Its bits must all arrive within about one destination clock period of each other. Otherwise the synchroniser may see a mixture of old and new bits.

set_max_delay -datapath_only 3.0 -from [get_cells wptr_gray_reg*] -to [get_cells wptr_sync1_reg*]

-datapath_only means: ignore the clocks altogether, and just measure the data path against 3.0 ns.

All three pass, and the spread between the fastest and the slowest bit is 1.50 ns. What the constraint really protects is that spread, so the synchroniser never sees two bits change far apart.

Min delay

set_min_delay is the hold-side partner: the path must take at least this long. A path that can take as little as 0.10 + 0.15 = 0.25 ns, under set_min_delay -datapath_only 0.40, fails by 0.15 ns.

8.5 Case analysis and disabling arcs

Case analysis tells the tool a signal is held constant, so paths that cannot happen in that mode are not timed. Disabling a timing arc removes one arc from every path, which is how a combinational loop is broken.

Many chips have more than one mode. The commonest example is a test mode, where a multiplexer in front of each flip-flop switches from the normal logic to a long test path.

# functional mode
set_case_analysis 0 [get_ports test_mode]

# test mode, in a separate run with the test clock
set_case_analysis 1 [get_ports test_mode]

With the mode pin held at 0, the tool knows every test-mode multiplexer passes its functional input. The test paths disappear from the functional run. They are checked in a run of their own, in test mode, against the slower test clock.

Disabling a timing arc

A combinational loop is logic that feeds back on itself with no flip-flop in the way. A timing tool cannot add delays around a circle forever, so it has to cut the loop somewhere. It picks a place, and warns you. Better to choose the place yourself:

set_disable_timing -from A -to Y [get_cells u_loop_nand]

That arc is then left out of every path, everywhere. Use it sparingly, and only on arcs that really cannot carry a timed signal.

What you learned

• A false path is never timed; declare one only for paths that can never matter.
• A setup multicycle of N moves the hold check too; it needs an (N-1)-cycle hold multicycle.
• Between two clocks, count cycles of the faster one: -end for slow-to-fast, -start for fast-to-slow.
• set_max_delay -datapath_only bounds a crossing between unrelated clocks, such as a Gray pointer.
• set_min_delay is its hold-side partner.
• Case analysis removes paths that cannot happen in a mode; each mode needs its own run.
• Disabling a timing arc cuts it out of every path, and is how combinational loops are broken.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• False path
• Timing exception
• Multicycle path
• Max delay and min delay
• Case analysis
• Combinational loop

Practice

Interview corner

Volume 09 meets a different kind of storage element: the latch, which can borrow time from the next stage when a path runs late.