Advanced Memory Architectures & FIFO Engineering

module fifo_sync #(
  parameter DW = 8,
  parameter AW = 4                    // depth = 2**AW
) (
  input  wire          clk,
  input  wire          rst_n,
  input  wire          wr_en,
  input  wire [DW-1:0] wdata,
  input  wire          rd_en,
  output wire [DW-1:0] rdata,
  output wire          full,
  output wire          empty,
  output wire [AW:0]   count
);

  localparam DEPTH = 1 << AW;

  reg [DW-1:0] mem [0:DEPTH-1];

  // ONE BIT WIDER than the address - the extra bit is the lap counter.
  reg [AW:0] wptr, rptr;

  // Qualify the enables so a write when full (or read when empty) is a
  // harmless no-op rather than silent corruption.
  wire do_wr = wr_en && !full;
  wire do_rd = rd_en && !empty;

  always @(posedge clk)
    if (do_wr) mem[wptr[AW-1:0]] <= wdata;

  // Combinational read: data is available the moment it is written
  // ("first-word fall-through"). Register this for block RAM instead,
  // at the cost of one cycle of read latency.
  assign rdata = mem[rptr[AW-1:0]];

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      wptr <= {(AW+1){1'b0}};
      rptr <= {(AW+1){1'b0}};
    end else begin
      if (do_wr) wptr <= wptr + 1'b1;
      if (do_rd) rptr <= rptr + 1'b1;
    end
  end

  // Completely equal -> nothing in flight.
  assign empty = (wptr == rptr);

  // Same address, different lap -> writer has lapped the reader.
  assign full  = (wptr[AW] != rptr[AW]) &&
                 (wptr[AW-1:0] == rptr[AW-1:0]);

  // Subtraction wraps correctly in two's complement, so this is exact.
  assign count = wptr - rptr;

endmodule

module fifo_async #(
  parameter DW = 8,
  parameter AW = 4                    // depth = 2**AW  (MUST be a power of 2)
) (
  // ---- write domain ----
  input  wire          wclk,
  input  wire          wrst_n,
  input  wire          wr_en,
  input  wire [DW-1:0] wdata,
  output reg           wfull,
  // ---- read domain ----
  input  wire          rclk,
  input  wire          rrst_n,
  input  wire          rd_en,
  output wire [DW-1:0] rdata,
  output reg           rempty
);

  localparam DEPTH = 1 << AW;

  reg [DW-1:0] mem [0:DEPTH-1];

  // ================= WRITE DOMAIN ======================================
  reg  [AW:0] wbin, wgray;
  wire [AW:0] wbin_next  = wbin + (wr_en & ~wfull);
  wire [AW:0] wgray_next = wbin_next ^ (wbin_next >> 1);   // binary -> Gray

  always @(posedge wclk or negedge wrst_n)
    if (!wrst_n) begin
      wbin  <= {(AW+1){1'b0}};
      wgray <= {(AW+1){1'b0}};
    end else begin
      wbin  <= wbin_next;
      wgray <= wgray_next;
    end

  // BINARY pointer addresses the memory; only the GRAY one ever crosses.
  always @(posedge wclk)
    if (wr_en && !wfull) mem[wbin[AW-1:0]] <= wdata;

  // ================= READ DOMAIN =======================================
  reg  [AW:0] rbin, rgray;
  wire [AW:0] rbin_next  = rbin + (rd_en & ~rempty);
  wire [AW:0] rgray_next = rbin_next ^ (rbin_next >> 1);

  always @(posedge rclk or negedge rrst_n)
    if (!rrst_n) begin
      rbin  <= {(AW+1){1'b0}};
      rgray <= {(AW+1){1'b0}};
    end else begin
      rbin  <= rbin_next;
      rgray <= rgray_next;
    end

  assign rdata = mem[rbin[AW-1:0]];

  // ================= POINTER SYNCHRONIZERS =============================
  (* ASYNC_REG = "TRUE" *) reg [AW:0] wgray_s1, wgray_s2;   // wgray into rclk
  always @(posedge rclk or negedge rrst_n)
    if (!rrst_n) begin wgray_s1 <= {(AW+1){1'b0}}; wgray_s2 <= {(AW+1){1'b0}}; end
    else         begin wgray_s1 <= wgray;          wgray_s2 <= wgray_s1;       end

  (* ASYNC_REG = "TRUE" *) reg [AW:0] rgray_s1, rgray_s2;   // rgray into wclk
  always @(posedge wclk or negedge wrst_n)
    if (!wrst_n) begin rgray_s1 <= {(AW+1){1'b0}}; rgray_s2 <= {(AW+1){1'b0}}; end
    else         begin rgray_s1 <= rgray;          rgray_s2 <= rgray_s1;       end

  // ================= FLAGS (registered) ================================
  // EMPTY: the read pointer has caught the write pointer exactly.
  wire rempty_next = (rgray_next == wgray_s2);

  always @(posedge rclk or negedge rrst_n)
    if (!rrst_n) rempty <= 1'b1;        // a FIFO powers up empty
    else         rempty <= rempty_next;

  // FULL: the write pointer is one whole lap ahead. In Gray, that is the
  // read pointer with its TOP TWO bits inverted.
  wire wfull_next = (wgray_next ==
                     {~rgray_s2[AW:AW-1], rgray_s2[AW-2:0]});

  always @(posedge wclk or negedge wrst_n)
    if (!wrst_n) wfull <= 1'b0;
    else         wfull <= wfull_next;

endmodule

// ---- Small table -> combinational logic (a LUT tree) --------------------
// Perfectly fine up to a few dozen entries. Above that it explodes.
module rom_case (
  input  wire [3:0] addr,
  output reg  [6:0] seg          // 7-segment decoder
);
  always @(*) begin
    case (addr)
      4'h0: seg = 7'h3F;  4'h1: seg = 7'h06;
      4'h2: seg = 7'h5B;  4'h3: seg = 7'h4F;
      4'h4: seg = 7'h66;  4'h5: seg = 7'h6D;
      4'h6: seg = 7'h7D;  4'h7: seg = 7'h07;
      4'h8: seg = 7'h7F;  4'h9: seg = 7'h6F;
      default: seg = 7'h00;      // every path assigned -> no latch
    endcase
  end
endmodule


// ---- Large table -> initialised block RAM ------------------------------
module rom_bram #(
  parameter AW   = 10,
  parameter DW   = 16,
  parameter INIT = "coeffs.hex"
) (
  input  wire          clk,
  input  wire [AW-1:0] addr,
  output reg  [DW-1:0] data
);
  reg [DW-1:0] mem [0:(1<<AW)-1];

  // On an FPGA the bitstream carries these values, so the memory powers up
  // already loaded. On an ASIC this initial block is NOT synthesizable --
  // there you instantiate a compiled ROM macro or synthesize the table
  // into logic instead.
  initial $readmemh(INIT, mem);

  always @(posedge clk)
    data <= mem[addr];           // registered read -> block RAM
endmodule