Block RAM, FIFOs & Memory Inference

module sp_bram #(
  parameter int AW = 10,          // 1024 words
  parameter int DW = 32
) (
  input  logic          clk,
  input  logic          en,
  input  logic          we,
  input  logic [AW-1:0] addr,
  input  logic [DW-1:0] din,
  output logic [DW-1:0] dout
);

  // The array. No initial value needed - an FPGA's memory contents come
  // from the bitstream, so an uninitialised array powers up as zeros.
  logic [DW-1:0] mem [0:(1<<AW)-1];

  always_ff @(posedge clk) begin
    if (en) begin
      if (we) mem[addr] <= din;
      dout <= mem[addr];          // registered read - THE critical line
    end
  end

endmodule

module bram_byte_en (
  input  logic        clk,
  input  logic [3:0]  wstrb,       // one bit per byte lane
  input  logic [9:0]  addr,
  input  logic [31:0] din,
  output logic [31:0] dout
);

  logic [31:0] mem [0:1023];

  // Load contents at configuration time. The file is read at SYNTHESIS
  // time and baked into the bitstream - it is not a runtime operation.
  initial $readmemh("boot_rom.hex", mem);

  // A generate loop over byte lanes maps onto the BRAM's native write
  // enable pins. Writing this as a single masked assignment
  //   mem[addr] <= (din & mask) | (mem[addr] & ~mask);
  // creates a read-modify-write and destroys inference.
  always_ff @(posedge clk) begin
    for (int i = 0; i < 4; i++)
      if (wstrb[i]) mem[addr][i*8 +: 8] <= din[i*8 +: 8];
    dout <= mem[addr];
  end

endmodule

// ---- WRITE_FIRST -----------------------------------------------------
// The write is described BEFORE the read, and dout takes din directly.
always_ff @(posedge clk)
  if (en) begin
    if (we) begin
      mem[addr] <= din;
      dout      <= din;        // new data forwarded to the output
    end else
      dout <= mem[addr];
  end

// ---- READ_FIRST ------------------------------------------------------
// The read is unconditional; it sees the array as it was before the write.
always_ff @(posedge clk)
  if (en) begin
    if (we) mem[addr] <= din;
    dout <= mem[addr];         // old contents
  end

// ---- NO_CHANGE -------------------------------------------------------
// The read happens ONLY when not writing, so dout simply holds.
always_ff @(posedge clk)
  if (en) begin
    if (we) mem[addr] <= din;
    else    dout <= mem[addr];
  end

// Simple dual-port, independent clocks. This is the workhorse: a stream
// crossing from one clock domain into another through a shared buffer.
module sdp_bram #(
  parameter int AW = 9,           // 512 words
  parameter int DW = 64           // 64 bits - fits ONE tile as SDP
) (
  input  logic          wr_clk,
  input  logic          wr_en,
  input  logic [AW-1:0] wr_addr,
  input  logic [DW-1:0] wr_data,

  input  logic          rd_clk,
  input  logic          rd_en,
  input  logic [AW-1:0] rd_addr,
  output logic [DW-1:0] rd_data
);

  (* ram_style = "block" *)
  logic [DW-1:0] mem [0:(1<<AW)-1];

  // Write port - one clock
  always_ff @(posedge wr_clk)
    if (wr_en) mem[wr_addr] <= wr_data;

  // Read port - a DIFFERENT clock. The BRAM handles this natively;
  // the array itself needs no synchroniser. What DOES need one is the
  // control logic that decides rd_addr is safe to use.
  always_ff @(posedge rd_clk)
    if (rd_en) rd_data <= mem[rd_addr];

endmodule

// Asynchronous FIFO, 512 x 32, first-word-fall-through.
// No IP catalogue, no .xci file - this is the whole instantiation.
xpm_fifo_async #(
  .FIFO_MEMORY_TYPE   ("block"),   // block | distributed | ultra | auto
  .FIFO_WRITE_DEPTH   (512),
  .WRITE_DATA_WIDTH   (32),
  .READ_DATA_WIDTH    (32),
  .READ_MODE          ("fwft"),    // "fwft" or "std"
  .FIFO_READ_LATENCY  (0),         // must be 0 when READ_MODE is fwft
  .CDC_SYNC_STAGES    (3),         // 2 is the minimum; 3 for high MTBF
  .PROG_FULL_THRESH   (500),
  .PROG_EMPTY_THRESH  (10),
  .USE_ADV_FEATURES   ("0707"),    // enables prog_full/prog_empty/counts
  .ECC_MODE           ("no_ecc")
) u_fifo (
  .rst           (wr_rst),         // async assert, sync deassert to wr_clk

  .wr_clk        (wr_clk),
  .wr_en         (wr_en),
  .din           (wr_data),
  .full          (full),
  .prog_full     (almost_full),
  .wr_data_count (wr_count),

  .rd_clk        (rd_clk),
  .rd_en         (rd_en),
  .dout          (rd_data),
  .empty         (empty),
  .prog_empty    (almost_empty),
  .rd_data_count (rd_count),

  // Tie off what you do not use - leaving them unconnected is legal
  // but makes the synthesis log noisy.
  .injectsbiterr (1'b0), .injectdbiterr (1'b0),
  .sleep         (1'b0),
  .sbiterr       (), .dbiterr        (),
  .overflow      (), .underflow      (),
  .wr_ack        (), .data_valid     (),
  .almost_full   (), .almost_empty   (),
  .wr_rst_busy   (), .rd_rst_busy    ()
);

// A 4096 x 64 simple dual-port RAM with single-error-correct,
// double-error-detect. Nothing you can write in plain RTL infers this.
xpm_memory_sdpram #(
  .MEMORY_SIZE        (262144),      // bits, not words
  .MEMORY_PRIMITIVE   ("block"),
  .WRITE_DATA_WIDTH_A (64),
  .READ_DATA_WIDTH_B  (64),
  .ADDR_WIDTH_A       (12),
  .ADDR_WIDTH_B       (12),
  .READ_LATENCY_B     (2),           // 2 = use the output register
  .ECC_MODE           ("both_encode_and_decode"),
  .CLOCKING_MODE      ("independent_clock")
) u_ram (
  .clka   (wr_clk), .ena  (wr_en), .wea (1'b1),
  .addra  (wr_addr), .dina (wr_data),

  .clkb   (rd_clk), .enb  (rd_en),
  .addrb  (rd_addr), .doutb (rd_data),

  // Report corrected and uncorrectable errors up to your status logic.
  .sbiterrb (ecc_corrected), .dbiterrb (ecc_fatal),

  .injectsbiterra (1'b0), .injectdbiterra (1'b0),
  .regceb (1'b1), .rstb (1'b0), .sleep (1'b0)
);