AXI4, AXI4-Lite & AXI-Stream

// Two-entry skid buffer. Fully registered in both directions and still
// sustains one transfer per cycle. This module is the single most
// reused block in any AXI design - write it once, instantiate it
// everywhere a timing path needs breaking.
module axis_skid #(parameter int W = 32) (
  input  logic         clk,
  input  logic         rstn,

  input  logic [W-1:0] s_tdata,
  input  logic         s_tvalid,
  output logic         s_tready,

  output logic [W-1:0] m_tdata,
  output logic         m_tvalid,
  input  logic         m_tready
);

  logic [W-1:0] skid_data;
  logic         skid_valid;

  // We can accept new data whenever the overflow slot is free. Note this
  // does NOT look at m_tready - that is what makes the path registered.
  assign s_tready = !skid_valid;

  always_ff @(posedge clk) begin
    if (!rstn) begin
      m_tvalid   <= 1'b0;
      skid_valid <= 1'b0;
    end
    // ---- output register is free to advance ---------------------------
    else if (!m_tvalid || m_tready) begin
      if (skid_valid) begin
        m_tdata    <= skid_data;    // drain the overflow slot first
        m_tvalid   <= 1'b1;
        skid_valid <= 1'b0;
      end else begin
        m_tdata  <= s_tdata;        // straight through
        m_tvalid <= s_tvalid;
      end
    end
    // ---- output stalled: catch whatever we already accepted -----------
    else if (s_tvalid && s_tready) begin
      skid_data  <= s_tdata;
      skid_valid <= 1'b1;
    end
  end

endmodule

module axil_regs (
  input  logic        clk,
  input  logic        rstn,

  // ---- write address channel ----
  input  logic [ 3:0] s_awaddr,
  input  logic        s_awvalid,
  output logic        s_awready,

  // ---- write data channel ----
  input  logic [31:0] s_wdata,
  input  logic [ 3:0] s_wstrb,
  input  logic        s_wvalid,
  output logic        s_wready,

  // ---- write response channel ----
  output logic [ 1:0] s_bresp,
  output logic        s_bvalid,
  input  logic        s_bready,

  // ---- read address channel ----
  input  logic [ 3:0] s_araddr,
  input  logic        s_arvalid,
  output logic        s_arready,

  // ---- read data channel ----
  output logic [31:0] s_rdata,
  output logic [ 1:0] s_rresp,
  output logic        s_rvalid,
  input  logic        s_rready,

  // ---- to the rest of the design ----
  output logic [31:0] cfg_a,
  output logic [31:0] cfg_b,
  output logic        start_pulse,
  input  logic [31:0] status
);

  localparam logic [1:0] RESP_OKAY = 2'b00;
  localparam logic [1:0] RESP_SLVERR = 2'b10;

  // Byte address 0x0, 0x4, 0x8, 0xC -> word index [3:2]
  logic [1:0] aw_word, ar_word;

  logic        aw_done, w_done;
  logic [ 3:0] awaddr_q;
  logic [31:0] wdata_q;
  logic [ 3:0] wstrb_q;

  assign aw_word = awaddr_q[3:2];
  assign ar_word = s_araddr[3:2];

  // RULE 2 in action: ready depends only on our own state, never on the
  // incoming valid. No combinational path from input to output.
  assign s_awready = !aw_done && !s_bvalid;
  assign s_wready  = !w_done  && !s_bvalid;
  assign s_arready = !s_rvalid;

  // ---- capture address and data on their own handshakes ---------------
  always_ff @(posedge clk) begin
    if (s_awvalid && s_awready) awaddr_q <= s_awaddr;
    if (s_wvalid  && s_wready ) begin
      wdata_q <= s_wdata;
      wstrb_q <= s_wstrb;
    end
  end

  // ---- write commit and response --------------------------------------
  always_ff @(posedge clk) begin
    if (!rstn) begin
      aw_done     <= 1'b0;
      w_done      <= 1'b0;
      s_bvalid    <= 1'b0;
      s_bresp     <= RESP_OKAY;
      cfg_a       <= 32'd0;
      cfg_b       <= 32'd0;
      start_pulse <= 1'b0;
    end else begin
      start_pulse <= 1'b0;              // one cycle wide, always

      if (s_awvalid && s_awready) aw_done <= 1'b1;
      if (s_wvalid  && s_wready ) w_done  <= 1'b1;

      // Both halves have arrived and no response is outstanding: commit.
      if (aw_done && w_done && !s_bvalid) begin
        s_bvalid <= 1'b1;
        s_bresp  <= RESP_OKAY;

        unique case (aw_word)
          2'd0: for (int i = 0; i < 4; i++)
                  if (wstrb_q[i]) cfg_a[i*8 +: 8] <= wdata_q[i*8 +: 8];
          2'd1: for (int i = 0; i < 4; i++)
                  if (wstrb_q[i]) cfg_b[i*8 +: 8] <= wdata_q[i*8 +: 8];
          2'd2: start_pulse <= wdata_q[0];   // command: self-clearing
          2'd3: s_bresp <= RESP_SLVERR;      // status is read-only
        endcase
      end

      // Response accepted: clear everything for the next transaction.
      if (s_bvalid && s_bready) begin
        s_bvalid <= 1'b0;
        aw_done  <= 1'b0;
        w_done   <= 1'b0;
      end
    end
  end

  // ---- read path -------------------------------------------------------
  always_ff @(posedge clk) begin
    if (!rstn) begin
      s_rvalid <= 1'b0;
      s_rresp  <= RESP_OKAY;
    end else if (s_arvalid && s_arready) begin
      s_rvalid <= 1'b1;
      s_rresp  <= RESP_OKAY;
      unique case (ar_word)
        2'd0: s_rdata <= cfg_a;
        2'd1: s_rdata <= cfg_b;
        2'd2: s_rdata <= 32'd0;          // command reads back as zero
        2'd3: s_rdata <= status;
      endcase
    end else if (s_rvalid && s_rready) begin
      s_rvalid <= 1'b0;
    end
  end

endmodule

// Split a transfer at the next 4KB boundary. Every custom AXI master
// needs this, and forgetting it is the classic first-bring-up failure.
function automatic logic [8:0] beats_to_boundary
  (input logic [31:0] addr, input int bytes_per_beat, input int want_beats);

  logic [31:0] bytes_left;
  int          max_beats;

  // How many bytes remain in this 4KB page?
  bytes_left = 32'h1000 - {20'd0, addr[11:0]};
  max_beats  = bytes_left / bytes_per_beat;

  // AXI4 also caps a single burst at 256 beats.
  if (max_beats > 256)        max_beats = 256;
  if (want_beats < max_beats) max_beats = want_beats;

  return max_beats[8:0];
endfunction

// Usage: awlen = beats_to_boundary(addr, 8, remaining) - 1;

// A minimal, correct AXI-Stream processing block: apply a gain and pass
// TLAST through. The whole art is the back-pressure handling.
module axis_gain (
  input  logic        clk,
  input  logic        rstn,
  input  logic [15:0] gain,        // from an AXI4-Lite register

  input  logic [31:0] s_tdata,
  input  logic        s_tvalid,
  input  logic        s_tlast,
  output logic        s_tready,

  output logic [31:0] m_tdata,
  output logic        m_tvalid,
  output logic        m_tlast,
  input  logic        m_tready
);

  // The single most important line in any stream block: accept input
  // only when the output can move. Everything else follows from it.
  assign s_tready = !m_tvalid || m_tready;

  always_ff @(posedge clk) begin
    if (!rstn) begin
      m_tvalid <= 1'b0;
    end else if (s_tready) begin
      m_tvalid <= s_tvalid;
      if (s_tvalid) begin
        // Sideband travels WITH the beat it belongs to. Registering
        // TLAST separately from TDATA is how frames get off by one.
        m_tdata <= (s_tdata * gain) >> 8;
        m_tlast <= s_tlast;
      end
    end
  end

endmodule