FPGA Mastery: Vivado, Zynq & Hardware Bring-Up
Simulation tells you your logic is right. Hardware tells you whether your constraints were right. This course covers everything between a working testbench and a board that actually does the thing - the fabric you are really targeting, synthesis and implementation, timing closure on real devices, AXI, the Zynq seam, and the debug loop for when it does not work the first time.
Start here
Work forward from Volume 01 - each volume depends only on the ones before it. If you already know the fabric and are here because a design will not close timing, go straight to §2.4 for how to read the report and Volume 03 for the constraints that are probably missing. If a board is on the bench and nothing works, start at §7.5.
always_ff, non-blocking assignment, FSM coding style and
reset strategy are automatic for you. If they are not, work through
Course 01 - Verilog & SystemVerilog
first. It is free, it is complete, and Volume 07 of it (static timing analysis) is the
single concept most FPGA beginners are missing when their design fails to meet timing.
Full syllabus
Part I - The target and the toolchain
- 01 FPGA Architecture from the Inside Out LUTs as SRAM truth tables, slice packing and control sets, the dedicated carry chain, distributed vs block vs UltraRAM, DSP48 pipelining, and the global clock network. Live
- 02 The Vivado Flow: Synthesis to Bitstream Elaboration vs synthesis, the optimisations that eat your synchroniser, attributes and directives, the opt/place/phys_opt/route contracts, reading reports, and a non-project Tcl build. Live
- 03 Constraints: XDC, Clocks & I/O Planning XDC ordering and silent empty matches, primary and generated clocks, asynchronous clock groups, input/output delay budgeting from a datasheet, timing exceptions, and pin planning. Live
Part II - Building real blocks
- 04 Block RAM, FIFOs & Memory Inference The templates that infer BRAM, read-first vs write-first vs no-change, true and simple dual-port, XPM FIFOs and first-word-fall-through, and when to instantiate a primitive instead. Live
- 05 AXI4, AXI4-Lite & AXI-Stream The VALID/READY rules and the deadlock they prevent, a full skid buffer, a compliant AXI4-Lite register slave in eighty lines, bursts and the 4KB rule, and AXI-Stream datapaths. Live
Part III - Silicon that is on your desk
- 06 Zynq: Processing System + Programmable Logic Zynq-7000 and MPSoC architecture, GP/HP/ACP ports and their real bandwidth, address maps and bare-metal drivers, DMA with cache maintenance, and fabric interrupts into the GIC. Live
- 07 On-Hardware Debug & Bring-Up ILA insertion and capture-memory budgeting, triggers and storage qualification, VIO and JTAG-to-AXI, catching intermittent faults with sticky flags, and a six-step bring-up sequence. Live
What you need before starting
| Requirement | Why it matters | Free option |
|---|---|---|
| Synthesizable RTL fluency | Every volume assumes you can already write the logic | Course 01, volumes 01-08 |
| Static timing analysis basics | Setup, hold and slack are the vocabulary of the whole course | Course 01, Volume 07 |
| Vivado (any recent version) | You cannot learn implementation by reading reports you never ran | Vivado ML Standard Edition is free and supports most Artix and Zynq-7000 parts |
| A board - optional but transformative | Volumes 06 and 07 are about hardware that exists | Any Zynq-7000 board (Zybo, PYNQ-Z2, Cora Z7) or Artix board (Arty, Basys 3) |
| Basic C | Volume 06 writes a bare-metal driver | Only pointers and volatile are assumed |