State Machines from Zero: Design, Code, Test and Make Them Safe
A state machine is how a circuit remembers what it is doing. Traffic lights, lifts, vending machines and the receiver in every serial port are all state machines. This course starts from zero - no electronics and no code assumed. By the end you will design a state machine on paper, write it in Verilog, test it, make it safe, and explain it in an interview.
Start here
Start with Volume 00, even if you think you know the basics. It takes under an hour, and it teaches exactly the few ideas this course needs: bits, gates, flip-flops, timing diagrams, and how to run Verilog for free. Then go through the volumes in order. Each one uses only what came before it.
Every lesson is written in simple English. Each new word is underlined with dots - point at it (or tap it) to see what it means. Every sub-module ends with a quick check, so you always know whether an idea has landed before you move on.
Take the quick checks in Volume 00 and Volume 01 without reading the lessons. If you get them all right, jump to Volume 04, where the Verilog starts. For a shorter, faster treatment of the same topic, see Volume 04 of the Verilog course. This course is the slower, deeper version, with every step shown.
Full syllabus
Part I - The ideas, on paper
- 00 Start Here: What You Need Before State Machines How the course works, then the five ideas it needs: bits and gates, flip-flops, the clock, timing diagrams, and running Verilog free in a browser. Live
- 01 What Is a State Machine? Machines that remember, from a turnstile to a traffic light. States, inputs, outputs and transitions; drawing the state diagram and writing the state table; and why hardware needs a clock. Live
- 02 Moore, Mealy and Medvedev Machines The three ways a state machine can make its outputs, seen side by side on the same waveform - and how to turn one kind into another. Live
- 03 Designing a State Machine by Hand From a word problem to real gates: giving states binary codes, flip-flop excitation tables, next-state logic with K-maps, output logic, and one full worked design. Live
Part II - From paper to Verilog
- 04 Writing State Machines in Verilog and SystemVerilog The two-block template, the one-, two- and three-process styles, default assignments that stop latches, reset choices, SystemVerilog enums, and your first FSM testbench. Live
- 05 State Encoding: Binary, Gray, One-Hot and More How the same machine can store its state in different bit patterns - binary, Gray, one-hot, Johnson or your own - and what each choice costs in area, speed and power. Live
Part III - Building real machines
- 06 Sequence Detectors Masterclass The most-asked FSM problem, solved every way: overlapping and non-overlapping, Mealy and Moore, long and multiple patterns, divisibility checkers, and how to test a detector properly. Live
- 07 Counters, Timers and Debouncers as State Machines Every counter is a state machine. Mod-N, up/down, ring and Johnson counters; timers and timeouts inside an FSM; switch debouncing; pulse generators and edge detectors. Live
- 08 Real-World Controllers Six complete machines built step by step: a traffic light with timers, a vending machine that gives change, a lift controller, a UART, an SPI master and a bus handshake controller. Live
- 09 State Machines Working Together A controller plus a datapath (FSMD), ASM charts, machines inside machines, request/acknowledge handshakes, and two state machines on two different clocks. Live
Part IV - Better machines
- 10 State Minimisation and Equivalence Why fewer states matter, how to spot two states that do the same job, and the two classic methods - partitioning and the implication table - with GATE-style problems. Live
- 11 Safe and Fault-Tolerant State Machines What happens when a state machine lands in a state that should not exist - and how to make sure it always recovers: safe coding, tool settings, radiation upsets, Hamming codes and TMR. Live
- 12 Verifying State Machines Tests that visit every state and every arrow, state and transition coverage, assertions for FSMs, formal reachability in plain words, and how to debug a machine that is stuck. Live
- 13 State Machine Timing and Performance Registered and combinational outputs, glitch-free outputs, the critical path through an FSM, look-ahead and pipelined control, and how FPGA and ASIC targets change the design. Live
Part V - Revision and interviews
What you need before starting
| What | Why | Free option |
|---|---|---|
| Nothing but curiosity | Volume 00 teaches every idea the course uses | - |
| A web browser | To run Verilog without installing anything | EDA Playground (free account) |
| Optional: your own simulator | To work offline | Icarus Verilog and GTKWave, both free and open source |
| Optional: an FPGA board | To see your machine run on real hardware | Any small board works - the course never needs one |