FSM Studio
Fill in a state table. Watch the state diagram draw itself, get clean Verilog and a self-checking testbench, and run your machine one clock edge at a time.
New to state machines? Learn them from zero in our free course
1 Describe the machine
2 See it
3 Run it, one clock edge at a time
How to use FSM Studio
- Pick an example from the course, or press New.
- Name the inputs and outputs. Then fill in the state table: for every state and every input combination, choose the next state. Set the outputs for each state (Moore) or for each arrow (Mealy).
- The diagram, the Verilog, the testbench and the checks update as you go. Drag the states to tidy the diagram.
- Run the machine: set the inputs, press Clock edge, and watch the state, the outputs and the waveform. Take every arrow runs the shortest test that covers the whole table.
What the checks tell you
- Unreachable states can only be entered by an error, such as a flipped bit.
- No way back means that once the machine is there, only a reset brings it home.
- Equivalent states behave identically for every input, so they can be merged. Minimise does it for you, with the partition method.
- Convert turns a Mealy machine into a Moore machine, or back, the way the course teaches it.
Learn the theory
- States, arrows and state tables (Volume 01)
- Moore, Mealy and Medvedev machines (Volume 02)
- Writing FSMs in Verilog (Volume 04)
- Binary, Gray and one-hot encoding (Volume 05)
- State minimisation (Volume 10)
- Testing every transition (Volume 12)
Questions
Is the generated Verilog synthesizable?
Yes. It uses the standard two-block template: a clocked block for the state register and a combinational block for the next state, with default assignments so that no latches are built. It works in any FPGA or ASIC flow.
Is my state machine uploaded anywhere?
No. FSM Studio runs entirely in your browser. Your machine is kept in the page address, so the address itself is the share link, and in your browser's local storage.
What is the difference between a Moore and a Mealy machine?
A Moore machine's outputs depend only on its current state. A Mealy machine's outputs also depend on the current inputs, so they can respond one clock cycle sooner, often with fewer states. The Checks tab converts one into the other.
Guide
Designing with FSM Studio, from table to tested Verilog
A finite state machine is a circuit that remembers where it is in a job - one of a fixed number of states - and moves to a new state at each clock edge depending on its inputs. FSM Studio lets you describe one the way engineers write them down, as a state table, and then does the tedious parts for you: it draws the diagram, writes the Verilog, builds a testbench, and lets you step through the machine one clock edge at a time.
The sections below walk through one complete example, then explain each of the design choices the studio offers.
A worked example: detecting the pattern 101The built-in "101 detector, Moore" example, explained
The job: watch a stream of bits on input x, one per clock, and set output
z to 1 whenever the last three bits were 1, 0, 1. Choose 101 detector, Moore
from the example list to load it.
The trick is to name each state after how much of the pattern has been seen so far:
| State | Meaning | z | next if x = 0 | next if x = 1 |
|---|---|---|---|---|
| S0 | nothing useful yet | 0 | S0 | S1 |
| S1 | seen "1" | 0 | S10 | S1 |
| S10 | seen "10" | 0 | S0 | S101 |
| S101 | seen "101" - match! | 1 | S10 | S1 |
Look at the last row. After a match, a 0 goes to S10, not S0, because the final "1" of "101" can be the first "1" of the next match. That is called overlapping detection.
Feeding in 1101011 takes the machine through S1, S1, S10, S101, S10, S101, S1, so
z reads 0001010: two matches, sharing a 1 in the middle. We checked this table
against a brute-force search on every input string up to 12 bits long - all 8,190 of them.
The table has 4 states and 2 possible input values, so it has 8 arrows. Take every arrow builds the shortest test that uses each one at least once.
Moore or Mealy?Where the outputs come from
In a Moore machine the outputs belong to the states: z is 1 because the
machine is in S101. In a Mealy machine the outputs belong to the arrows: the
output depends on the state and the input right now.
- A Mealy machine usually needs fewer states - the 101 detector needs three instead of four - and reacts one clock cycle sooner.
- A Moore machine's outputs change only at clock edges, so they are steadier and easier to time.
The Checks tab can convert one kind into the other, so you can compare both versions of the same design.
Encoding, reset and outputs: the Verilog optionsWhat each setting changes in the generated hardware
State encoding
Each state is stored as a pattern of flip-flop values. Binary numbers the states 0, 1, 2, and so on, using the fewest flip-flops. Gray uses the same number of flip-flops but lets neighbouring codes differ in one bit. One-hot uses one flip-flop per state, exactly one of them set.
| States | Binary or Gray | One-hot |
|---|---|---|
| 4 | 2 flip-flops | 4 |
| 5 | 3 | 5 |
| 8 | 3 | 8 |
| 12 | 4 | 12 |
| 16 | 4 | 16 |
One-hot costs more flip-flops but makes the next-state logic very simple. FPGAs have flip-flops to spare, so one-hot is often the faster choice there.
Synchronous or asynchronous reset
A synchronous reset takes effect at the next clock edge; an asynchronous one acts immediately. Either way, the machine goes to the state you mark in the table's Reset column. The generated code also sends any unused state code back to that state, so a flipped bit cannot leave the machine stuck.
Decoded or registered outputs
Decoded outputs are worked out from the state by logic, so they can glitch briefly while the state bits change. Registered outputs are stored in their own flip-flops, so they change cleanly at the clock edge - the safer choice when an output drives something outside the chip.
Testing your machineThe testbench, coverage and running it in a simulator
- In Run it, set the inputs and press Clock edge to step the machine. The state, the outputs and a waveform update each time, and the coverage shows which arrows you have used.
- In the Testbench tab, choose Take every arrow for the shortest test that covers the whole table, or Replay my run to turn your own steps into a test.
- The testbench checks every output it expects and reports any mismatch, so it tells you whether the design passed rather than leaving you to read waveforms.
- Copy the design and the testbench into a free online simulator such as EDA Playground, choose a Verilog simulator, and run it.
The Checks tab also looks for design mistakes: states that can never be reached from reset, states the machine can never leave to get back home without a reset, and pairs of states that behave identically and can be merged. Minimise merges them for you.
Saving and sharing a design
Your machine is stored in the page address itself, so Copy share link gives a link that reopens exactly this design - handy for sending to a lab partner or pasting into a report. It is also kept in your browser's storage, so it is still there if you close the tab. Designs can have up to 16 states, 3 inputs and 4 outputs.
The ideas behind every option here are taught step by step in State Machines from Zero, starting with what a state machine is.