Course 03 Free · No signup 6 volumes · 30 sub-modules ~24 hours

ASIC & Physical Design Flow (OpenLane / Sky130)

What actually happens between your Verilog and a manufactured chip. Every step in this course runs on genuinely free, open-source tooling against the SkyWater 130 nm PDK - so you can execute the whole RTL-to-GDSII flow on a laptop, with no EDA licence and no NDA. Nothing is pre-built here: you place every cell, build the clock tree, and route every wire.

Why this course can exist at all Until 2020 this material was unteachable outside a university with an EDA licence. Google and SkyWater open-sourced a real, manufacturable 130 nm PDK, and OpenLane wraps Yosys, OpenROAD, Magic and Netgen into a complete flow. Every command in these six volumes is one you can run tonight. The node is mature rather than leading-edge - and every concept transfers directly to the 7 nm flow you will meet later under NDA.

Start here

Work forward from Volume 01 - the flow is a pipeline and each volume is a stage that consumes the previous one's output. If you already know the flow and are here for a specific problem: congestion and utilisation are in §3.1, hold violations after CTS in §4.5, and why post-route timing degraded in §5.5.

This is the most advanced course in the Academy It assumes you can write clean synthesizable RTL and that setup, hold and slack are vocabulary rather than concepts. If not, work through Course 01 - Verilog & SystemVerilog first, especially its Volume 07 on static timing analysis. Course 02 - FPGA Mastery is not a prerequisite, but it covers the same ideas against a fixed fabric and makes an excellent warm-up.

Full syllabus

Part I - Inputs and the netlist

Part II - Turning a netlist into geometry

Part III - Proving it

06 Sign-Off: STA, DRC & LVS Multi-corner multi-mode analysis and OCV derating, OpenSTA against real parasitics, DRC and density fill with Magic, LVS with Netgen, and a twelve-item tape-out checklist. Live

What you need before starting

Requirement	Why it matters	Free option
Synthesizable RTL fluency	The flow starts with a netlist; this course never teaches you to write one	Course 01, volumes 01-08
Static timing analysis	Setup, hold and slack are assumed vocabulary from Volume 01 onward	Course 01, Volume 07
CMOS device intuition	Latch-up, IR drop and antenna rules are device physics, not logic	Developed from first principles where needed
OpenLane + Sky130	Reading a flow you never run teaches very little	Docker image plus `open_pdks`, both free; ~20 GB of disk
Comfort with Tcl	Every tool in the flow is driven by it	The scripts in each volume are annotated line by line

All six volumes are live - and that completes the Academy Three courses, 24 volumes, 117 sub-modules, free and with no signup. Together they cover the entire path from your first always block to a GDSII file a foundry will accept. The best next step is to run the flow on something you wrote yourself. Subscribe on YouTube for what comes after.