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Volume 05 Advanced 5 sub-modules ~55 min read

Routing & Parasitic Extraction

Routing is where estimates end. Every previous stage worked with a model of interconnect; now there is actual metal, with actual resistance and capacitance, and static timing analysis finally has something true to analyse. The number that comes out is usually worse than the one you have been quoting for the last three stages - and understanding exactly why is the difference between reacting to that and predicting it.

5.1 The metal stack

A chip is a sandwich: transistors at the bottom, then a stack of metal layers separated by insulator, connected vertically by vias. Sky130 gives you a local interconnect layer plus five metals, and they are not interchangeable.

Cross-section of the Sky130 metal stack from transistors through local interconnect and five metal layers, showing increasing thickness and decreasing resistance higher in the stack HIGHER = THICKER = LOWER RESISTANCE = FEWER TRACKS silicon: transistors, poly, diffusion li1 cell pins only met1 horiz · rails met2 vert met3 horiz · long nets met4 vert · PDN met5 horiz · PDN, clk one net: up the stack for the long haul, back down to the pin sheet resistance falls alternating preferred directions is what makes any point reachable from any other
Figure 5.1 - The Sky130 stack. Layers alternate horizontal and vertical preferred direction; each via costs resistance, so the router trades layer-jumping against the lower resistance of going higher.
Layer Preferred direction Relative pitch Mostly used for
li1 Vertical (local only) Finest Standard cell pins - the router lands here and leaves
met1 Horizontal Fine Cell power rails, very short connections
met2 Vertical Fine General signal routing
met3 Horizontal Medium General signals, medium-length nets
met4 Vertical Coarse Power straps, long nets
met5 Horizontal Coarsest Power ring and straps, top-level clock
Why preferred directions exist at all If every layer routed in every direction, two nets on the same layer would need to cross, and they cannot. Alternating horizontal and vertical means any Manhattan path is constructible with one via per turn, and it makes the track supply computable - which is exactly what the congestion analysis in §4.2 was counting. Routing against the preferred direction is legal but expensive, and a router doing a lot of it is a router in trouble.

5.2 Global, track and detailed routing

Routing a million nets simultaneously and exactly is intractable, so it is decomposed the same way placement was: solve it coarsely, then refine.

Stage Decides Granularity Output
Global routing Which coarse tiles (GCells) each net passes through A grid of tiles, each many tracks wide A route plan and a congestion map
Track assignment Which specific track within a layer each long segment uses Individual tracks Straight segments, not yet connected
Detailed routing Exact geometry, every via, every jog Manufacturing grid A DRC-clean, fully connected layout

Global routing is where you find out whether the floorplan was viable. It reports overflow: tiles where more nets want to cross than there are tracks available. Small, scattered overflow is normal and detailed routing will absorb it. Large contiguous regions of overflow mean detailed routing will run for hours and then fail, and the honest response is to go back to §3.1 rather than to try router settings. 


# Which layers signals may use. Reserving met5 (and often met4) for the
# power grid is normal - but every layer you reserve is track supply the
# signal router does not have.
set ::env(RT_MIN_LAYER) "met1"
set ::env(RT_MAX_LAYER) "met4"

# Deliberate pessimism given to the global router: pretend fewer tracks
# exist than really do, so it spreads nets out and leaves detailed
# routing room to manoeuvre. 0.15 = "assume 15% of tracks are gone".
set ::env(GRT_ADJUSTMENT) 0.15

# Let the router rip up and reroute more aggressively when it is stuck.
set ::env(ROUTING_OPT_ITERS) 64

# Symptom -> response:
#   scattered overflow      -> raise GRT_ADJUSTMENT slightly, carry on
#   one dense overflow blob -> a floorplan or RTL problem, not a router one
#   DRC errors after detail -> usually pin access: cells too tightly packed

5.3 Antenna violations and diodes

This is the one physical-design rule that has nothing to do with electrical behaviour of the finished chip. It is about damage inflicted during manufacturing, and it catches every newcomer because the layout looks perfectly correct.

Metal layers are patterned in a plasma etch. Plasma is charged, and an exposed metal segment collects that charge. If the segment is connected to a transistor gate but not yet to any diffusion, the charge has nowhere to go: voltage builds across the gate oxide, which at 130 nm is only a few nanometres thick. Enough charge ruptures it.

Why it is a build-order problem
Antenna ratio AR  =  area of connected metal  /  area of connected gate
The layers are built bottom up. When met2 is being etched, met3 does not exist yet - so a met2 segment that will eventually reach a diffusion contact via met3 is, at etch time, a large isolated collector attached to a tiny gate. The PDK specifies a maximum ratio per layer. Exceed it and the transistor may be damaged before the chip is even finished.
Fix How it works Cost
Layer jumping Break the long run: go up to a higher layer for the middle section and back down. The lower segment attached to the gate is now short Two extra vias, a little resistance. Usually the first choice
Diode insertion Attach a reverse-biased diode to the gate node. During etch it leaks the charge into the substrate; in normal operation it is off A cell site plus a little capacitance on the net
Buffer insertion Splitting the net also splits the metal, and the buffer's output is a diffusion node A real cell, real delay - but it may have been wanted anyway 

# Two strategies. Both are legitimate; the trade is area against runtime.

# 1. Fix reactively: route, check, insert diodes only where needed.
set ::env(DIODE_INSERTION_STRATEGY) 3   ;# OpenROAD's repair_antennas

# 2. Fix pre-emptively: place a fake diode on every cell input up front,
#    then swap the unused ones for filler. Costs area, but converges in
#    one pass rather than several.
# set ::env(DIODE_INSERTION_STRATEGY) 2
# set ::env(DIODE_CELL) "sky130_fd_sc_hd__diode_2"

# Verify afterwards - this is a sign-off check, not an optimisation.
#   check_antennas

5.4 RC extraction and SPEF

With metal on the die, the parasitics are finally computable. Extraction walks the routed geometry and, for every net, produces a resistance and capacitance network: resistance from the metal's sheet resistance and its length, capacitance to the substrate below, to the plates above, and - critically - to the neighbouring wires alongside.

A routed wire modelled as a distributed resistor-capacitor ladder, with coupling capacitance to a neighbouring aggressor net A WIRE IS AN RC LADDER, NOT A NODE driver R R R R ground capacitance: to substrate and to the plates above load neighbouring net (aggressor) coupling C crosstalk lives here t ≈ 0.38 · R · C   with R ∝ L and C ∝ L so wire delay ∝ L² - double the length, quadruple the delay
Figure 5.4 - Extraction turns each net into a distributed RC ladder plus coupling to its neighbours. Both R and C grow with length, so their product grows with the square of it.
The quadratic is why buffers exist A 2 mm wire has twice the resistance and twice the capacitance of a 1 mm wire, so roughly four times the delay. Cut it in half with a buffer and each segment has a quarter of the original delay: two quarters plus one buffer delay beats the whole. This is the entire reason long interconnect is buffered rather than widened - widening lowers R but raises C, and gains far less than splitting does. It is also why the FPGA course could ignore all of this: on an FPGA the buffers are already in the routing fabric, pre-placed.

The result is written to SPEF - one entry per net, with its resistors, ground capacitors and coupling capacitors. STA reads it and computes real wire delay instead of an estimate. 


*SPEF "IEEE 1481-1998"
*DESIGN "counter"
*T_UNIT 1 PS
*C_UNIT 1 FF
*R_UNIT 1 OHM

*D_NET net_1247 18.4304        // total capacitance of this net, in fF

*CONN
*I *3251:A  I *L 0.0024        // an input pin (a load)
*I *1180:X  O *D sky130_fd_sc_hd__buf_2   // the driver

*CAP
1 *3251:A            4.1102    // node capacitance to ground
2 net_1247:2         6.8871
3 net_1247:2 net_998:4  2.9014 // COUPLING to another net -> crosstalk

*RES
1 *1180:X  net_1247:2   118.4  // ohms of metal between driver and node
2 net_1247:2 *3251:A     94.7

*END

5.5 Why post-route timing changes

Here is the accounting. Your critical path has been quoted at four different numbers by four different stages, and each increase has a specific cause.

Stage Path delay What was newly modelled
Post-synthesis 6.20 ns Gate delay only. Wires assumed ideal or statistical
Post-placement 7.05 ns Estimated wire length from real cell positions
Post-CTS 7.35 ns Real clock skew and insertion delay replace the uncertainty guess
Post-route (SPEF) 8.10 ns Actual metal R and C, every via, detours around congestion
Post-route + SI 8.35 ns Crosstalk delta delay from coupling capacitance

Five contributors explain the 2.15 ns of growth, and each is a different lever:

Budget for the growth from the start Roughly 25-35% growth from post-synthesis to post-route is normal on a mature node with a reasonable floorplan. That is exactly why §2.5 recommended synthesising against a period 10-20% tighter than the real target. If your growth is much larger than this, the cause is nearly always congestion forcing long detours - and that sends you back to the floorplan, not to the router.
Interview grilling - "How would you fix a post-route path that is 70% wire delay?"

The split between cell delay and net delay is the diagnosis, and 70% net says the problem is distance, not logic. Work from cheapest to most disruptive:

  • Buffer the long net. The quadratic means splitting a long wire in half is a large win. This is the first thing post-route optimisation tries, and often the only thing needed.
  • Promote it to a higher metal layer. met4 has far lower sheet resistance than met1. Costs two vias, and the net has to be important enough to justify the track.
  • Widen and space it. Non-default routing rules lower R and cut coupling capacitance. Standard practice for clock nets and long buses.
  • Move the endpoints closer. If the two cells are on opposite sides of the die, no amount of wire engineering fixes it - the placement or the floorplan is wrong, and that is a much bigger conversation.
  • Pipeline it. If the distance is genuinely irreducible, add a register stage. This is an RTL change with an architectural consequence - an extra cycle of latency - so it is the last resort and it needs the front-end team.

The point that separates a strong answer: "I would also check whether the path is long because of congestion detours rather than genuine distance. Those look identical in the timing report but have completely different fixes."

Volume 05 recap

Concept The one thing to remember
Metal stack Higher = thicker = lower R, but coarser pitch and fewer tracks.
Preferred direction Alternating H and V is what makes routing solvable.
Global route overflow Scattered is fine. One dense blob is a floorplan problem.
Antenna rule Damage during etch, not in operation. Jump layers or add a diode.
Wire delay Grows with L². Buffer, do not widen.
SPEF R, ground C and coupling C per net. Sign-off needs it.
Post-route growth 25-35% is normal. Much more means detours.
Crosstalk Coupling C makes a neighbour's switching your delay.
Previous Vol 04 - Placement & CTS Next Vol 06 - Sign-Off: STA, DRC & LVS