What is a good core utilisation for an ASIC floorplan?

For a first pass on a standard cell design, 50 to 60 per cent is a sensible target. The remaining area is not waste: it holds the buffers that clock tree synthesis will insert, the cells that timing optimisation will add, and the space the router needs for wires. Designs with heavy interconnect or many macros often need 35 to 45 per cent, while very regular datapath-style blocks can exceed 70.

What are tap cells and why does a design need them?

Tap cells tie the n-well to the supply and the p-substrate to ground. Without them the well and substrate float, and the parasitic bipolar structures inherent in CMOS can trigger latch-up, which shorts supply to ground and destroys the chip. The PDK specifies a maximum distance between taps, so they are inserted on a regular pitch across every standard cell row before placement begins.

Why does IR drop matter for timing?

Cell delay depends on supply voltage, and the power grid has resistance, so a cell far from a supply connection sees less than the nominal voltage. A five per cent IR drop can slow a cell by roughly ten to fifteen per cent. Since timing was signed off at the nominal voltage in the Liberty file, a design with significant IR drop is slower than static timing analysis reported, and the failure appears only under heavy switching activity.

Volume 03 Advanced 5 sub-modules ~55 min read

Floorplanning & Power Distribution

The floorplan is the first physical decision and the one every later stage inherits. Choose the area too small and no amount of placement effort will route it. Put a macro in the wrong place and the datapath has to walk around it for the rest of the project. And build the power grid badly and the chip will be slower than static timing analysis ever told you - because STA assumed a supply voltage the silicon never actually sees.

3.1 Core area, utilisation and aspect ratio

Three numbers define the canvas. Everything else in this volume is spent inside them.

Figure 3.1 - Die, core and rows. The empty space between cells is working area: it holds the clock buffers CTS has not inserted yet, the cells optimisation will add, and the wires the router still has to fit.

Utilisation	Suits	What goes wrong
30-40%	Congested designs, many macros, heavy interconnect	Wastes silicon; long wires between distant cells
50-60%	The default starting point for standard cell logic	Usually nothing - begin here and adjust on evidence
65-75%	Regular datapath, low fanout, few macros	CTS and optimisation run out of room to insert buffers
> 80%	Almost nothing	Routing congestion, unfixable timing, failed legalisation

Utilisation is a routing decision disguised as an area decision Cells occupy the lower metal layers with their own internal wiring and pins. The router needs the layers above and horizontal room to get in and out. Pack cells tighter and you do not merely run out of placement sites - you run out of routing tracks, and the symptom is a router that runs for hours and then reports thousands of unrouted nets. When that happens, the fix is almost always a lower utilisation, not a cleverer router setting.


# OpenLane: let the tool derive the area from utilisation ...
set ::env(FP_SIZING)      "relative"
set ::env(FP_CORE_UTIL)   45          ;# per cent
set ::env(FP_ASPECT_RATIO) 1

# ... or pin it absolutely, which is what you do when the die size is
# fixed by the package or by a shuttle programme's tile size.
# set ::env(FP_SIZING)  "absolute"
# set ::env(DIE_AREA)   "0 0 900 900"    ;# microns

# Space between the core and the I/O ring: room for the power ring and
# for pin-to-core routing. Too small and the ring has nowhere to go.
set ::env(FP_IO_HMETAL) 4
set ::env(FP_IO_VMETAL) 3
set ::env(FP_IO_MODE)   1             ;# 1 = spread pins evenly

# The placer's own density target. Keep it at or slightly above
# FP_CORE_UTIL/100; setting it far higher re-creates the congestion you
# just paid area to avoid.
set ::env(PL_TARGET_DENSITY) 0.50

3.2 Macro placement and blockages

A macro is anything the placer cannot move freely inside a row: an SRAM, a PLL, an analogue block, a hardened processor core. Macros are placed by hand, before anything else, and the choice is architectural rather than mechanical.

Rule	Why
Push macros to the edges, keep the centre for logic	A macro in the middle splits the core in two and every net crossing it must detour
Face the pins toward the logic that uses them	Macro pins are on fixed sides. Rotating a memory so its data bus faces its consumer can save thousands of long wires
Leave a routing channel between adjacent macros	Two macros abutted create a corridor with no tracks. Everything must go round
Add a halo (keep-out) around each macro	Cells crammed against a macro edge have nowhere for their own wires to escape
Group macros that talk to each other	Wire length between them is fixed the moment you place them; no later stage can fix it

Blockages are how you tell the tools where they may not work, and there are three kinds worth distinguishing:

Placement blockage - no standard cells here. Used under a macro's overhang, or to reserve a channel.
Routing blockage - no wires on these layers here. Used over an analogue block that must not be crossed by noisy digital signals.
Halo - a soft margin travelling with the macro. Move the macro and the halo moves too, which is why it beats a hand-drawn blockage rectangle.

Macro placement is effectively irreversible Every later stage - placement, CTS, routing - optimises within the floorplan it is given. None of them will move a macro. If the timing report after routing shows a 4 ns path that is 90% wire between two blocks on opposite corners of the die, no optimisation setting will recover it; you have to go back to the floorplan and start the whole flow again. Spend the extra hour up front.

3.3 The power distribution network

Every one of your million cells needs V_DD and V_SS. Delivering them is not a routing problem the router solves - the PDN is built deliberately, before signal routing, as a hierarchy from the pads down to the cell rails.

Figure 3.3 - The PDN hierarchy. The cell rails at the bottom come free from row abutment; everything above them is built by the flow, consumes routing resource, and is the reason you cannot floorplan at 90% utilisation.


# Wider straps and tighter pitch = less IR drop, but they eat the routing
# tracks your signals need. This is the central trade-off of the PDN.

set ::env(FP_PDN_VWIDTH)  2.0    ;# vertical strap width, um
set ::env(FP_PDN_HWIDTH)  2.0    ;# horizontal strap width
set ::env(FP_PDN_VPITCH) 50.0    ;# spacing between vertical straps
set ::env(FP_PDN_HPITCH) 50.0

set ::env(FP_PDN_VOFFSET) 16.5
set ::env(FP_PDN_HOFFSET) 16.5

# Core ring: the collar the straps hang off.
set ::env(FP_PDN_CORE_RING)         1
set ::env(FP_PDN_CORE_RING_VWIDTH)  3.0
set ::env(FP_PDN_CORE_RING_HWIDTH)  3.0

# Symptom -> fix:
#   IR drop too high        -> wider straps, or tighter pitch
#   routing congestion      -> narrower straps, or looser pitch
#   both at once            -> the core is too small. Go back to 3.1.

3.4 Tap cells, endcaps and the latch-up problem

Some cells have no logic function at all and are inserted purely to keep the silicon alive. They are easy to skip past in a flow script and they are not optional.

A CMOS inverter sits in a p-substrate with an n-well for the PMOS. Those regions form parasitic bipolar transistors - a PNP and an NPN - cross-coupled into a structure that behaves like a thyristor. If a transient ever forward-biases it, it latches on: a low-resistance path opens from V_DD straight to ground and stays open until the power is removed, usually taking the chip with it.

The defence is to tie the well and substrate firmly to the rails so they cannot float. That is a tap cell, and the PDK specifies a maximum distance between them.

Physical-only cell	Job	Consequence of omitting it
Tap / well-tie	Ties n-well to V_DD, p-substrate to V_SS	Latch-up risk; DRC failure on well-tie spacing
Endcap / boundary	Terminates each row so well geometry is legal at the edge	DRC violations along every row end
Decap	On-chip capacitance between the rails	Supply droops during simultaneous switching; dynamic IR drop
Filler	Fills gaps so the implant and well layers stay continuous	DRC failures in the gaps between cells
Antenna diode	Discharges long metal during fabrication	Gate oxide damage - covered in Volume 05


# Distance between tap cells, in microns. This number comes from the PDK
# latch-up rule - it is not a preference. Sky130's hd library wants
# taps no more than ~13 um apart, so a 14 um pitch with staggered rows
# gives margin.
set ::env(FP_TAPCELL_DIST) 14

set ::env(FP_WELLTAP_CELL) "sky130_fd_sc_hd__tapvpwrvgnd_1"
set ::env(FP_ENDCAP_CELL)  "sky130_fd_sc_hd__decap_3"

# Insertion happens BEFORE placement - taps occupy sites, and the placer
# needs to know that when it decides where everything else goes.

Decaps are not filler with a fancy name When ten thousand flops switch on the same clock edge, they draw a current spike the power grid cannot supply instantly - the supply droops for a few hundred picoseconds. Decoupling capacitors distributed through the rows act as local reservoirs that ride out the spike. A design with no decaps can pass static IR-drop analysis and still fail on silicon at exactly the moment of peak activity, which is precisely when timing is tightest.

3.5 IR drop and electromigration

The power grid is metal, and metal has resistance. Current flowing through it produces a voltage drop, so a cell in the middle of the die sees less than the nominal supply. This is IR drop, and it matters because it is a timing problem that static timing analysis cannot see.

Why a 5% supply drop is not a 5% problem

Alpha-power law, roughly t_pd ∝ V_DD / (V_DD − V_th)^α

Delay depends on the overdrive V_DD − V_th, not on V_DD itself. At 1.8 V with a threshold near 0.5 V, losing 90 mV removes about 7% of the overdrive and costs roughly 10-15% of speed in that region. STA read its numbers from a Liberty file characterised at the full 1.80 V, so every path through that region is slower than the report says - and nothing in the timing flow will tell you.

	Static IR drop	Dynamic IR drop
Driven by	Average current, including leakage	Peak switching current on a clock edge
Depends on	Grid resistance alone	Grid resistance and local decoupling capacitance
Typical budget	< 2-3% of V_DD	< 5% of V_DD
Fix	Wider straps, tighter pitch, more via stacks	More decaps, and spread the switching in time
Worst case	Furthest point from a supply pad	Densest region of simultaneously switching flops

Electromigration: the grid wears out

The second failure mode is slower and permanent. At high current density, momentum transfer from flowing electrons physically displaces metal atoms. Over months or years, material migrates away from one point until the wire opens - or piles up until it shorts to a neighbour. The chip works perfectly, ships, and fails in the field after eighteen months.

Risk is driven by current density (A per unit cross-section), so it hits narrow wires carrying large currents - power straps and clock nets, not ordinary signals.
It is strongly temperature-accelerated, which is why EM sign-off is done at the maximum junction temperature, not at typical.
Vias are the usual weak point: a single via has a far lower current limit than the wide wire either side of it. This is why PDN via stacks are drawn as arrays.

Interview grilling - "Timing closed post-route, but the chip fails at speed. Where do you look?"

The premise says timing closed, so the fault is in an assumption STA made rather than in a path it analysed. Four candidates, and the first is the one this volume is about:

IR drop. STA used the nominal voltage from the Liberty file. If the real supply sags 5% in the busiest region, every cell there is 10-15% slower. Run a dynamic IR-drop analysis and overlay the hot spots on the critical paths - if they coincide, that is your answer.
Crosstalk. A quiet net switched by an aggressive neighbour picks up delay or a glitch. Signal-integrity-aware STA models this; basic STA does not.
Clock tree behaviour across corners. Skew that is benign at typical can grow at the extremes, eroding the margin a fixed uncertainty number assumed.
Missing or wrong constraints. An unconstrained path was never analysed, so "timing closed" was a statement about a subset of the design.

The framing that earns the point: "Closing timing means the design is consistent with the models. Failing silicon means one of the models was wrong. So I would go looking for the assumption, not for a slow path."

Volume 03 recap

Concept	The one thing to remember
Utilisation	Start at 50-60%. The empty space is for CTS and the router.
Congestion	Usually an area problem, not a router setting.
Macros	Edges, pins facing the logic, channels between. Effectively irreversible.
PDN	Ring → straps → rails. Wider straps cost routing tracks.
Tap cells	Latch-up prevention. Pitch comes from the PDK, not from you.
Decaps	Local charge reservoirs for the switching spike. Not filler.
IR drop	5% supply loss ≈ 10-15% speed loss, invisible to STA.
Electromigration	Current density, not current. Vias fail first.