Course 01 Free · No signup 11 volumes · 52 sub-modules ~40 hours

Verilog & SystemVerilog Silicon Masterclass

The complete path from your first always block to closing timing on a real design. Every volume contrasts three things explicitly: what the simulator does, what the synthesis tool builds, and what an interviewer will grill you on.

Start here

If you have never written HDL before, begin at Volume 01 and work forward - the volumes are ordered so that each one only depends on the ones before it. If you are revising for an interview in the next 48 hours, skip straight to Volume 10 (formula vault and rapid drills) and Volume 11 (the interview vault).

How to actually learn this Read the theory, then copy the RTL into a simulator and break it deliberately. Change a <= to =, delete a default branch, remove a reset - then look at what the waveform and the synthesis report say. The bugs you cause on purpose are the ones you will recognise instantly in an interview.

Full syllabus

Part I - Foundations

Part II - Industrial design

Part III - SystemVerilog

Part IV - Interview preparation

What you need before starting

Requirement	Why it matters	Free option
Boolean algebra & K-maps	Every combinational block reduces to this	Any first-year digital logic text
A Verilog simulator	You cannot learn HDL by reading alone	Icarus Verilog + GTKWave, or EDA Playground in-browser
Basic CMOS intuition	Volume 01 starts at the transistor	Covered from first principles in §1.1

All eleven volumes are live The course is complete - 11 volumes, 52 sub-modules, free and with no signup. If you are revising for an interview, start at Volume 10 for the formula vault and 50 flashcards, then Volume 11 for 40 worked interview problems. When you are ready to put this RTL on real silicon, continue to Course 02 - FPGA Mastery, which is also complete. Subscribe on YouTube for the next course.