SystemVerilog for Design (IEEE 1800)

// The base type is NOT optional in practice. Without "logic [2:0]" an
// enum defaults to a 32-bit 2-state int - wasteful, and it loses X
// propagation on your state register.
typedef enum logic [2:0] {
  S0    = 3'd0,
  S1    = 3'd1,
  S10   = 3'd2,
  S101  = 3'd3,
  S1011 = 3'd4
} state_e;

state_e state, next_state;

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) state <= S0;
  else        state <= next_state;

always_comb begin
  next_state = state;
  unique case (state)          // "unique" asks the tool to check overlap
    S0   : next_state = din ? S1    : S0;
    S1   : next_state = din ? S1    : S10;
    S10  : next_state = din ? S101  : S0;
    S101 : next_state = din ? S1011 : S10;
    S1011: next_state = din ? S1    : S10;
  endcase
end

// Enums carry methods. This prints "S101", not "3".
always_ff @(posedge clk)
  if (trace_en) $display("state = %s", state.name());

typedef struct packed {
  logic        valid;      // bit 36  - first declared = most significant
  logic [3:0]  id;         // bits 35:32
  logic [31:0] data;       // bits 31:0
} pkt_t;                   // 37 bits total

// A whole bundle crosses a module boundary as ONE port.
module sink (
  input  logic clk,
  input  pkt_t pkt_in
);
  always_ff @(posedge clk)
    if (pkt_in.valid)
      $display("id=%0d data=%h", pkt_in.id, pkt_in.data);
endmodule

// Because it is packed, all of these are legal and mean the same thing:
//   pkt.data        pkt[31:0]        pkt_t'(37'h1_0000_00FF)
//
// Adding a field to pkt_t updates every module that uses it. No port
// lists to edit, nothing to get out of step.

// COMBINATIONAL - the tool errors if this could infer a latch.
always_comb begin
  next_state = state;            // default first (Volume 1.5 still applies)
  case (state)
    IDLE: if (start) next_state = RUN;
    RUN : if (done)  next_state = IDLE;
    default: next_state = IDLE;
  endcase
end

// SEQUENTIAL - the tool errors if this is not a flip-flop.
always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) count <= '0;       // '0 fills the whole width with zeros
  else if (en) count <= count + 1'b1;
end

// LATCH - deliberately. Declaring it makes review trivial: an
// always_latch is a decision, an inferred latch is an accident.
always_latch begin
  if (gate) q_held <= d;
end

interface apb_if #(
  parameter int AW = 32,
  parameter int DW = 32
) (
  input logic pclk,
  input logic presetn
);

  logic [AW-1:0] paddr;
  logic          psel, penable, pwrite;
  logic [DW-1:0] pwdata, prdata;
  logic          pready, pslverr;

  // A modport is a VIEW of the same signals with directions applied.
  modport master (
    input  pclk, presetn, prdata, pready, pslverr,
    output paddr, psel, penable, pwrite, pwdata
  );

  modport slave (
    input  pclk, presetn, paddr, psel, penable, pwrite, pwdata,
    output prdata, pready, pslverr
  );

endinterface


// The module declares a ROLE, not eight ports.
module apb_slave (apb_if.slave bus);

  always_ff @(posedge bus.pclk or negedge bus.presetn) begin
    if (!bus.presetn) begin
      bus.prdata <= '0;
      bus.pready <= 1'b0;
    end else begin
      bus.pready <= bus.psel && bus.penable;
      if (bus.psel && bus.penable && !bus.pwrite)
        bus.prdata <= regfile[bus.paddr[7:2]];
    end
  end

endmodule

package chip_pkg;

  localparam int ADDR_W = 32;
  localparam int DATA_W = 64;

  typedef enum logic [1:0] { IDLE, BUSY, DONE, ERROR } state_e;

  typedef struct packed {
    logic              valid;
    logic [3:0]        id;
    logic [DATA_W-1:0] data;
  } pkt_t;

  // Functions in packages must be `automatic` - a static function would
  // share one set of locals across every concurrent call.
  function automatic logic [3:0] parity_nibble(input logic [15:0] v);
    return {^v[15:12], ^v[11:8], ^v[7:4], ^v[3:0]};
  endfunction

endpackage


// Three ways to reach into it - pick one and be consistent.
import chip_pkg::*;              // everything (convenient, can collide)
import chip_pkg::state_e;        // one name (explicit, verbose)
// chip_pkg::state_e s;          // fully qualified, no import at all

module core (
  input  logic       clk,
  input  chip_pkg::pkt_t pkt_in
);
  chip_pkg::state_e state;
  ...
endmodule

import chip_pkg::*;

state_e      s;
logic [1:0]  raw;

// STATIC cast - no check. If raw is not a legal encoding you now hold an
// enum variable containing a value the type says cannot exist.
s = state_e'(raw);

// DYNAMIC cast - returns 1 on success, 0 on failure. Used as a function
// it lets you handle the bad case instead of corrupting state.
if (!$cast(s, raw))
  $error("illegal state encoding: %0d", raw);

// Reading a register written by software is exactly this situation: the
// value came from outside the design and cannot be trusted to be legal.