Clock Domain Crossing & Reset Synchronizers

module sync_2ff #(
  parameter STAGES = 2,        // 3 for very high frequency domains
  parameter INIT   = 1'b0      // value held during reset
) (
  input  wire clk_dst,
  input  wire rst_n,
  input  wire din_async,       // from another clock domain
  output wire dout
);

  // ASYNC_REG tells the place-and-route tool to keep these flops adjacent,
  // which maximises the settling time actually available to FF1.
  (* ASYNC_REG = "TRUE" *) reg [STAGES-1:0] sync;

  always @(posedge clk_dst or negedge rst_n)
    if (!rst_n) sync <= {STAGES{INIT}};
    else        sync <= {sync[STAGES-2:0], din_async};

  assign dout = sync[STAGES-1];

endmodule

// Crossing a ONE-CYCLE PULSE from a fast domain into a slow one.
// Trick: a pulse cannot survive the crossing, but a LEVEL CHANGE can.
// So toggle a flop on each pulse, synchronize the level, and rebuild the
// pulse on the far side with an edge detector.

module pulse_sync (
  input  wire clk_src,
  input  wire rst_n_src,
  input  wire pulse_in,        // 1 cycle wide in clk_src

  input  wire clk_dst,
  input  wire rst_n_dst,
  output wire pulse_out        // 1 cycle wide in clk_dst
);

  // ---- source: pulse -> level change -----------------------------------
  reg toggle;
  always @(posedge clk_src or negedge rst_n_src)
    if (!rst_n_src)   toggle <= 1'b0;
    else if (pulse_in) toggle <= ~toggle;

  // ---- destination: 3 flops. Two to synchronize, one to remember the
  //      previous value so we can detect the edge. ------------------------
  (* ASYNC_REG = "TRUE" *) reg [2:0] sync;
  always @(posedge clk_dst or negedge rst_n_dst)
    if (!rst_n_dst) sync <= 3'b000;
    else            sync <= {sync[1:0], toggle};

  // Either edge of the toggle means "one pulse happened".
  assign pulse_out = sync[2] ^ sync[1];

endmodule

// ---------- SOURCE SIDE ------------------------------------------------
module cdc_handshake_src #(
  parameter W = 8
) (
  input  wire         clk_src,
  input  wire         rst_n,
  input  wire         send,          // request a transfer
  input  wire [W-1:0] din,
  input  wire         ack_sync,      // ack, already synced INTO clk_src
  output reg          busy,
  output reg          req,
  output reg  [W-1:0] data_held      // crosses UNSYNCHRONIZED, on purpose
);

  always @(posedge clk_src or negedge rst_n) begin
    if (!rst_n) begin
      req <= 1'b0; busy <= 1'b0; data_held <= {W{1'b0}};
    end else if (!busy && send) begin
      // Capture and FREEZE the data, then raise req. Because data_held
      // cannot change again until the whole handshake completes, the
      // destination can read it with no synchronizer at all.
      data_held <= din;
      req       <= 1'b1;             // phase 1
      busy      <= 1'b1;
    end else if (busy && req && ack_sync) begin
      req <= 1'b0;                   // phase 3: ack seen, drop req
    end else if (busy && !req && !ack_sync) begin
      busy <= 1'b0;                  // phase 4 complete, ready for the next
    end
  end

endmodule


// ---------- DESTINATION SIDE -------------------------------------------
module cdc_handshake_dst #(
  parameter W = 8
) (
  input  wire         clk_dst,
  input  wire         rst_n,
  input  wire         req_sync,      // req, already synced INTO clk_dst
  input  wire [W-1:0] data_held,     // stable by protocol, not by synchronizer
  output reg  [W-1:0] dout,
  output reg          valid,
  output reg          ack
);

  always @(posedge clk_dst or negedge rst_n) begin
    if (!rst_n) begin
      ack <= 1'b0; valid <= 1'b0; dout <= {W{1'b0}};
    end else begin
      valid <= 1'b0;                 // single-cycle pulse

      if (req_sync && !ack) begin
        // req has come through 2 flops, so data_held has been stable for
        // at least two destination clocks. Safe to sample directly.
        dout  <= data_held;
        valid <= 1'b1;
        ack   <= 1'b1;               // phase 2
      end else if (!req_sync && ack) begin
        ack <= 1'b0;                 // phase 4
      end
    end
  end

endmodule

# CDC paths must be excluded from normal timing analysis - the tool would
# otherwise try (and fail) to close timing between unrelated clocks.

# Tell STA the two clocks have no phase relationship at all.
set_clock_groups -asynchronous \
  -group [get_clocks clk_src] \
  -group [get_clocks clk_dst]

# Bound the crossing wire anyway: keep the source-flop-to-FF1 delay short so
# FF1 gets the maximum possible settling time. A bare false_path would let
# the router make this arbitrarily long.
set_max_delay -datapath_only \
  -from [get_cells src_ff_reg] \
  -to   [get_cells {sync_inst/sync_reg[0]}] 4.0