Synthesizable Combinational Logic & Arithmetic Datapaths

// ---- Style A: indexed part-select. Scales to any N without editing. ------
module mux_n #(
  parameter W = 8,          // width of each channel
  parameter N = 4           // number of channels
) (
  input  wire [N*W-1:0]       din,   // flattened: { ch3, ch2, ch1, ch0 }
  input  wire [$clog2(N)-1:0] sel,
  output wire [W-1:0]         dout
);
  // "Starting at bit sel*W, take W bits going up." Synthesizes to a MUX.
  assign dout = din[sel*W +: W];
endmodule


// ---- Style B: explicit case. Clearest when channels have real names. ----
module mux4_case #(
  parameter W = 8
) (
  input  wire [W-1:0] d0, d1, d2, d3,
  input  wire [1:0]   sel,
  output reg  [W-1:0] y
);
  always @(*) begin
    case (sel)
      2'd0:    y = d0;
      2'd1:    y = d1;
      2'd2:    y = d2;
      2'd3:    y = d3;
      // sel is 2 bits, so all four values are already covered. The default
      // is unreachable - assigning X tells synthesis "I do not care",
      // which lets it optimise. It also guarantees no latch (Volume 1.5).
      default: y = {W{1'bx}};
    endcase
  end
endmodule


// ---- Style C: structural tree, built from 2:1 primitives ----------------
module mux2 #(
  parameter W = 8
) (
  input  wire [W-1:0] a, b,
  input  wire         s,
  output wire [W-1:0] y
);
  assign y = s ? b : a;
endmodule

module mux4_tree #(
  parameter W = 8
) (
  input  wire [W-1:0] d0, d1, d2, d3,
  input  wire [1:0]   sel,
  output wire [W-1:0] y
);
  wire [W-1:0] lo, hi;

  // Both first-level MUXes evaluate CONCURRENTLY - 2 levels deep, not 3.
  mux2 #(W) u_lo  (.a(d0), .b(d1), .s(sel[0]), .y(lo));
  mux2 #(W) u_hi  (.a(d2), .b(d3), .s(sel[0]), .y(hi));
  mux2 #(W) u_out (.a(lo), .b(hi), .s(sel[1]), .y(y));
endmodule

module priority_encoder_8to3 (
  input  wire [7:0] req,
  output reg  [2:0] grant,
  output wire       valid    // 0 => no request, grant is meaningless
);

  assign valid = |req;       // OR-reduction: any bit set?

  always @(*) begin
    // casez treats ? in the PATTERN as don't-care. The first matching
    // branch wins, which is exactly the priority semantics we want.
    casez (req)
      8'b1???????: grant = 3'd7;   // bit 7 highest priority
      8'b01??????: grant = 3'd6;
      8'b001?????: grant = 3'd5;
      8'b0001????: grant = 3'd4;
      8'b00001???: grant = 3'd3;
      8'b000001??: grant = 3'd2;
      8'b0000001?: grant = 3'd1;
      8'b00000001: grant = 3'd0;
      default:     grant = 3'd0;   // req == 0; `valid` tells you to ignore it
    endcase
  end

endmodule

module full_adder (
  input  wire a, b, cin,
  output wire sum, cout
);
  assign sum  = a ^ b ^ cin;
  assign cout = (a & b) | (cin & (a ^ b));
endmodule


module ripple_carry_adder #(
  parameter W = 8
) (
  input  wire [W-1:0] a, b,
  input  wire         cin,
  output wire [W-1:0] sum,
  output wire         cout
);
  wire [W:0] c;
  assign c[0] = cin;

  genvar i;
  generate
    for (i = 0; i < W; i = i + 1) begin : g_bit
      full_adder u_fa (
        .a    (a[i]),
        .b    (b[i]),
        .cin  (c[i]),      // <-- THE PROBLEM: stage i waits for stage i-1
        .sum  (sum[i]),
        .cout (c[i+1])
      );
    end
  endgenerate

  assign cout = c[W];
endmodule

module cla_4bit (
  input  wire [3:0] a, b,
  input  wire       cin,
  output wire [3:0] sum,
  output wire       cout
);

  wire [3:0] g = a & b;     // generate: this bit makes a carry on its own
  wire [3:0] p = a ^ b;     // propagate: this bit passes a carry through
  wire [4:0] c;

  assign c[0] = cin;

  // Each carry is a FLAT expression of g, p and cin - no chaining.
  // Every one of these four lines evaluates at the same time.
  assign c[1] = g[0] | (p[0] & c[0]);

  assign c[2] = g[1] | (p[1] & g[0])
                     | (p[1] & p[0] & c[0]);

  assign c[3] = g[2] | (p[2] & g[1])
                     | (p[2] & p[1] & g[0])
                     | (p[2] & p[1] & p[0] & c[0]);

  assign c[4] = g[3] | (p[3] & g[2])
                     | (p[3] & p[2] & g[1])
                     | (p[3] & p[2] & p[1] & g[0])
                     | (p[3] & p[2] & p[1] & p[0] & c[0]);

  // Once the carries exist, the sums are one XOR each.
  assign sum  = p ^ c[3:0];
  assign cout = c[4];

endmodule

module alu #(
  parameter W = 32
) (
  input  wire [W-1:0] a,
  input  wire [W-1:0] b,
  input  wire [3:0]   op,
  output reg  [W-1:0] y,
  output wire         zero,
  output wire         negative,
  output wire         carry,
  output wire         overflow
);

  localparam ALU_ADD  = 4'd0, ALU_SUB  = 4'd1, ALU_SLL = 4'd2,
             ALU_SLT  = 4'd3, ALU_SLTU = 4'd4, ALU_XOR = 4'd5,
             ALU_SRL  = 4'd6, ALU_SRA  = 4'd7, ALU_OR  = 4'd8,
             ALU_AND  = 4'd9;

  localparam SHW = $clog2(W);          // 5 bits of shift amount for W = 32

  // ---- ONE shared adder serves ADD, SUB, SLT and SLTU ------------------
  wire is_sub = (op == ALU_SUB) | (op == ALU_SLT) | (op == ALU_SLTU);

  // Conditional inversion, no MUX: replicate the control bit and XOR.
  wire [W-1:0] b_in  = b ^ {W{is_sub}};
  wire [W:0]   sum_x = {1'b0, a} + {1'b0, b_in} + is_sub;
  wire [W-1:0] sum   = sum_x[W-1:0];

  assign carry    = sum_x[W];
  assign overflow = (a[W-1] == b_in[W-1]) & (sum[W-1] != a[W-1]);

  // Both comparisons fall out of the subtraction for free.
  wire lt_signed   = sum[W-1] ^ overflow;   // two's complement less-than
  wire lt_unsigned = ~carry;                // no carry out == borrow

  wire [SHW-1:0] shamt = b[SHW-1:0];

  always @(*) begin
    case (op)
      ALU_ADD, ALU_SUB : y = sum;
      ALU_SLL          : y = a << shamt;
      ALU_SLT          : y = {{(W-1){1'b0}}, lt_signed};
      ALU_SLTU         : y = {{(W-1){1'b0}}, lt_unsigned};
      ALU_XOR          : y = a ^ b;
      ALU_SRL          : y = a >> shamt;              // logical: shifts in 0
      ALU_SRA          : y = $signed(a) >>> shamt;    // arithmetic: sign extends
      ALU_OR           : y = a | b;
      ALU_AND          : y = a & b;
      default          : y = {W{1'b0}};   // every path assigns y -> no latch
    endcase
  end

  assign zero     = (y == {W{1'b0}});
  assign negative = y[W-1];

endmodule

module barrel_shift_right #(
  parameter W   = 8,
  parameter SHW = 3            // $clog2(W)
) (
  input  wire [W-1:0]   din,
  input  wire [SHW-1:0] shamt,
  input  wire           arith,  // 1 = arithmetic (replicate sign), 0 = logical
  output wire [W-1:0]   dout
);

  wire fill = arith & din[W-1];   // what gets shifted in at the top
  wire [W-1:0] stage [0:SHW];     // stage[0] = input, stage[SHW] = output

  assign stage[0] = din;

  genvar i;
  generate
    for (i = 0; i < SHW; i = i + 1) begin : g_stage
      // Stage i shifts by exactly 2**i, or not at all. (1<<i) is an
      // elaboration-time constant, so this is a plain MUX per bit.
      assign stage[i+1] = shamt[i]
        ? { {(1<<i){fill}}, stage[i][W-1 : (1<<i)] }
        : stage[i];
    end
  endgenerate

  assign dout = stage[SHW];

endmodule

module booth_multiplier #(
  parameter W = 8
) (
  input  wire                  clk,
  input  wire                  rst_n,
  input  wire                  start,
  input  wire signed [W-1:0]   multiplicand,
  input  wire signed [W-1:0]   multiplier,
  output wire signed [2*W-1:0] product,
  output reg                   busy,
  output reg                   done
);

  reg signed [W-1:0]  a;      // accumulator (high half of the result)
  reg signed [W-1:0]  q;      // multiplier, becomes the low half
  reg                 q_1;    // the phantom bit to the right of q
  reg signed [W-1:0]  m;      // multiplicand
  reg [$clog2(W):0]   count;

  // Combinational: decide this step's operation from the Booth pair.
  reg signed [W-1:0] a_next;
  always @(*) begin
    case ({q[0], q_1})
      2'b01:   a_next = a + m;   // end of a run of ones   -> add
      2'b10:   a_next = a - m;   // start of a run of ones -> subtract
      default: a_next = a;       // 00 or 11               -> nothing
    endcase
  end

  assign product = {a, q};

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      a <= 0; q <= 0; q_1 <= 1'b0; m <= 0;
      count <= 0; busy <= 1'b0; done <= 1'b0;
    end else begin
      done <= 1'b0;                       // single-cycle pulse

      if (start && !busy) begin
        a     <= 0;
        q     <= multiplier;
        q_1   <= 1'b0;
        m     <= multiplicand;
        count <= W;
        busy  <= 1'b1;
      end else if (busy) begin
        // ARITHMETIC shift right of the whole {a, q, q_1} register.
        // a's MSB is replicated - that is what keeps signs correct.
        a     <= {a_next[W-1], a_next[W-1:1]};
        q     <= {a_next[0],   q[W-1:1]};
        q_1   <= q[0];
        count <= count - 1'b1;

        if (count == 1) begin
          busy <= 1'b0;
          done <= 1'b1;
        end
      end
    end
  end

endmodule

module divider_restoring #(
  parameter W = 8
) (
  input  wire         clk,
  input  wire         rst_n,
  input  wire         start,
  input  wire [W-1:0] dividend,
  input  wire [W-1:0] divisor,
  output wire [W-1:0] quotient,
  output wire [W-1:0] remainder,
  output reg          busy,
  output reg          done
);

  reg [W-1:0]       q;      // holds the dividend, becomes the quotient
  reg [W-1:0]       d;      // divisor
  reg [W:0]         r;      // remainder, one extra bit for the trial subtract
  reg [$clog2(W):0] count;

  // Shift the next dividend bit into the remainder, then TRY to subtract.
  wire [W:0] shifted = {r[W-1:0], q[W-1]};
  wire [W:0] diff    = shifted - {1'b0, d};

  assign quotient  = q;
  assign remainder = r[W-1:0];

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      r <= 0; q <= 0; d <= 0; count <= 0; busy <= 1'b0; done <= 1'b0;
    end else begin
      done <= 1'b0;

      if (start && !busy) begin
        r <= 0; q <= dividend; d <= divisor;
        count <= W; busy <= 1'b1;
      end else if (busy) begin
        if (diff[W] == 1'b0) begin      // no borrow: the subtraction fit
          r <= diff;
          q <= {q[W-2:0], 1'b1};        // quotient bit is 1
        end else begin                  // borrow: RESTORE the old remainder
          r <= shifted;
          q <= {q[W-2:0], 1'b0};        // quotient bit is 0
        end

        count <= count - 1'b1;
        if (count == 1) begin busy <= 1'b0; done <= 1'b1; end
      end
    end
  end

endmodule

module comparator #(
  parameter W      = 8,
  parameter SIGNED = 0
) (
  input  wire [W-1:0] a, b,
  output wire         gt, eq, lt
);

  assign eq = (a == b);

  generate
    if (SIGNED) begin : g_signed
      assign lt = ($signed(a) <  $signed(b));
      assign gt = ($signed(a) >  $signed(b));
    end else begin : g_unsigned
      assign lt = (a < b);
      assign gt = (a > b);
    end
  endgenerate

endmodule

module parity #(
  parameter W = 32
) (
  input  wire [W-1:0] data,
  output wire         even_parity_bit,  // append this to make the total even
  output wire         odd_parity_bit    // append this to make the total odd
);

  // ^ is XOR-reduction: 1 when data contains an ODD number of ones.
  // Synthesis builds a balanced XOR tree - log2(W) deep, not W.
  assign even_parity_bit = ^data;
  assign odd_parity_bit  = ~^data;

endmodule