Sequential Circuit Design & Edge-Triggered Realities

// ---- Plain positive-edge D flip-flop ------------------------------------
module dff (
  input  wire clk,
  input  wire d,
  output reg  q
);
  always @(posedge clk)
    q <= d;
endmodule


// ---- Negative-edge triggered -------------------------------------------
module dff_neg (
  input  wire clk,
  input  wire d,
  output reg  q
);
  // Legal, but mixing edge polarities in one design complicates timing
  // closure. Production RTL is almost always single-edge.
  always @(negedge clk)
    q <= d;
endmodule


// ---- Flop with a clock ENABLE (not a gated clock!) ---------------------
module dff_en (
  input  wire clk,
  input  wire en,
  input  wire d,
  output reg  q
);
  // The clock runs FREELY. The enable feeds a MUX in front of the D pin,
  // or maps to the flop's dedicated CE pin. This is the correct way to
  // "stop" a register - never by gating the clock in RTL.
  always @(posedge clk)
    if (en) q <= d;
    // No else: holding the old value IS the intended behaviour, and in a
    // clocked block that is a flop, not an inferred latch.
endmodule


// ---- SYNCHRONOUS active-low reset --------------------------------------
module dff_sync_rst (
  input  wire clk,
  input  wire rst_n,
  input  wire d,
  output reg  q
);
  // rst_n is NOT in the sensitivity list - it is just data that happens
  // to win. Nothing happens without a clock edge.
  always @(posedge clk)
    if (!rst_n) q <= 1'b0;
    else        q <= d;
endmodule


// ---- ASYNCHRONOUS active-low reset -------------------------------------
module dff_async_rst (
  input  wire clk,
  input  wire rst_n,
  input  wire d,
  output reg  q
);
  // The reset edge is in the sensitivity list, so the flop clears the
  // instant rst_n falls - no clock required.
  always @(posedge clk or negedge rst_n)
    if (!rst_n) q <= 1'b0;
    else        q <= d;
endmodule

module reset_sync #(
  parameter STAGES = 2            // 2 is standard; 3 for very high frequency
) (
  input  wire clk,                // destination clock domain
  input  wire arst_n,             // raw asynchronous reset, active low
  output wire rst_n               // clean reset for this clock domain
);

  reg [STAGES-1:0] sync;

  always @(posedge clk or negedge arst_n) begin
    if (!arst_n)
      sync <= {STAGES{1'b0}};     // ASSERT: asynchronous, immediate
    else
      sync <= {sync[STAGES-2:0], 1'b1};   // DE-ASSERT: shift a 1 through
  end

  assign rst_n = sync[STAGES-1];

endmodule

module counter_mod_n #(
  parameter N = 10,               // counts 0 .. N-1
  parameter W = $clog2(N)
) (
  input  wire         clk,
  input  wire         rst_n,
  input  wire         en,         // count enable
  input  wire         clr,        // synchronous clear
  input  wire         load,       // synchronous parallel load
  input  wire [W-1:0] load_val,
  output reg  [W-1:0] count,
  output wire         tc          // terminal count
);

  // TC asserts on the LAST value, while still enabled - so it can drive
  // the enable of the next counter in a cascade without losing a count.
  assign tc = en && (count == N-1);

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)      count <= {W{1'b0}};
    else if (clr)    count <= {W{1'b0}};    // clear beats load
    else if (load)   count <= load_val;     // load beats count
    else if (en) begin
      // Explicit wrap. Do NOT rely on natural rollover unless N is a
      // power of two - for N = 10 the counter would run to 15.
      if (count == N-1) count <= {W{1'b0}};
      else              count <= count + 1'b1;
    end
  end

endmodule

module gray_counter #(
  parameter W = 4
) (
  input  wire         clk,
  input  wire         rst_n,
  input  wire         en,
  output reg  [W-1:0] gray,
  output reg  [W-1:0] bin
);

  wire [W-1:0] bin_next  = bin + 1'b1;
  wire [W-1:0] gray_next = bin_next ^ (bin_next >> 1);

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      bin  <= {W{1'b0}};
      gray <= {W{1'b0}};
    end else if (en) begin
      bin  <= bin_next;
      gray <= gray_next;   // registered, so it is glitch-free at the output
    end
  end

endmodule

module shift_reg_universal #(
  parameter W = 8
) (
  input  wire         clk,
  input  wire         rst_n,
  input  wire [1:0]   mode,      // 00 hold, 01 shift right, 10 shift left, 11 load
  input  wire         sin_r,     // serial input for a right shift (enters MSB)
  input  wire         sin_l,     // serial input for a left shift  (enters LSB)
  input  wire [W-1:0] pin,       // parallel input
  output reg  [W-1:0] q
);

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= {W{1'b0}};
    else begin
      case (mode)
        2'b00: q <= q;                    // hold
        2'b01: q <= {sin_r, q[W-1:1]};    // shift right
        2'b10: q <= {q[W-2:0], sin_l};    // shift left
        2'b11: q <= pin;                  // parallel load
      endcase
    end
  end

endmodule

// NOTE: tap positions are specific to the register WIDTH - they come from
// a table of primitive polynomials (see below). So these modules are fixed
// at 8 bits on purpose. Parameterising the width without also swapping the
// taps would silently destroy the maximal-length property.

module lfsr8_fibonacci (
  input  wire       clk,
  input  wire       rst_n,
  input  wire       en,
  output reg  [7:0] lfsr
);

  wire feedback;

  // Polynomial x^8 + x^6 + x^5 + x^4 + 1.
  // Bit 8 of the polynomial is lfsr[7], bit 6 is lfsr[5], and so on.
  assign feedback = lfsr[7] ^ lfsr[5] ^ lfsr[4] ^ lfsr[3];

  always @(posedge clk or negedge rst_n) begin
    // The seed MUST be non-zero. Any non-zero value works and gives the
    // same cycle, just entered at a different point.
    if (!rst_n)  lfsr <= 8'hFF;
    else if (en) lfsr <= {lfsr[6:0], feedback};
  end

endmodule


// ---- Self-correcting variant: 256 states, including all-zeros ----------
module lfsr8_de_bruijn (
  input  wire       clk,
  input  wire       rst_n,
  input  wire       en,
  output reg  [7:0] lfsr
);

  // Inverting the feedback when the low 7 bits are all zero splices the
  // all-zero state into the cycle, giving a full 2^8-length sequence.
  // Now a zero seed is harmless - useful on FPGAs, where registers
  // power up to zero.
  wire feedback = lfsr[7] ^ lfsr[5] ^ lfsr[4] ^ lfsr[3] ^ (lfsr[6:0] == 7'b0);

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)  lfsr <= 8'h00;
    else if (en) lfsr <= {lfsr[6:0], feedback};
  end

endmodule

// What you should almost always do instead: ONE clock domain, and a
// periodic enable pulse that makes downstream logic advance every Nth cycle.
module tick_gen #(
  parameter N = 3
) (
  input  wire clk,
  input  wire rst_n,
  output wire tick        // one-cycle pulse, once every N clocks
);

  localparam W = $clog2(N);
  reg [W-1:0] cnt;

  assign tick = (cnt == N-1);

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)   cnt <= {W{1'b0}};
    else if (tick) cnt <= {W{1'b0}};
    else           cnt <= cnt + 1'b1;
  end

endmodule

// Downstream logic then reads:
//     always @(posedge clk) if (tick) ... ;
// Same clock everywhere. No new clock domain. No skew. Timing analysis
// stays trivial.

// Divide by 2: a single toggle flop. Duty cycle is exactly 50% by
// construction, because the output flips once per input rising edge.
module clk_div2 (
  input  wire clk,
  input  wire rst_n,
  output reg  clk_out
);
  always @(posedge clk or negedge rst_n)
    if (!rst_n) clk_out <= 1'b0;
    else        clk_out <= ~clk_out;
endmodule


// Divide by any EVEN N: count to N/2 - 1, then toggle.
module clk_div_even #(
  parameter N = 6                 // must be even
) (
  input  wire clk,
  input  wire rst_n,
  output reg  clk_out
);
  localparam HALF = N/2;
  localparam W    = $clog2(HALF);
  reg [W-1:0] cnt;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      cnt     <= {W{1'b0}};
      clk_out <= 1'b0;
    end else if (cnt == HALF-1) begin
      cnt     <= {W{1'b0}};
      clk_out <= ~clk_out;        // toggle every N/2 input clocks
    end else begin
      cnt     <= cnt + 1'b1;
    end
  end
endmodule

module clk_div_odd #(
  parameter N = 3                 // must be ODD and >= 3
) (
  input  wire clk,
  input  wire rst_n,
  output wire clk_out
);

  localparam W = $clog2(N);

  reg [W-1:0] pos_cnt, neg_cnt;

  // ---- counter clocked on the RISING edge -------------------------------
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)              pos_cnt <= {W{1'b0}};
    else if (pos_cnt == N-1) pos_cnt <= {W{1'b0}};
    else                     pos_cnt <= pos_cnt + 1'b1;
  end

  // ---- identical counter clocked on the FALLING edge --------------------
  // This is the only place in the whole course where a negedge block is
  // the right answer - it is what buys us the half-period offset.
  always @(negedge clk or negedge rst_n) begin
    if (!rst_n)              neg_cnt <= {W{1'b0}};
    else if (neg_cnt == N-1) neg_cnt <= {W{1'b0}};
    else                     neg_cnt <= neg_cnt + 1'b1;
  end

  // Each wave is high for (N-1) of N states - for N = 3 that is 2 of 3.
  wire pos_wave = (pos_cnt != N-1);
  wire neg_wave = (neg_cnt != N-1);

  // The AND trims exactly half a period off the high time:
  //   (N-1)T - 0.5T  =  N/2 * T   ->  exactly 50% duty.
  assign clk_out = pos_wave & neg_wave;

endmodule