Zynq: Processing System + Programmable Logic

#include "xparameters.h"
#include "xil_io.h"
#include "xil_cache.h"

/* Register map of the AXI4-Lite slave written in Volume 05. Offsets are
   byte addresses; the slave decoded bits [3:2] as the word index.       */
#define MYIP_BASE     XPAR_AXIL_REGS_0_S_AXI_BASEADDR   /* e.g. 0x43C00000 */
#define MYIP_CFG_A    0x00
#define MYIP_CFG_B    0x04
#define MYIP_CMD      0x08
#define MYIP_STATUS   0x0C

#define CMD_START     0x00000001u
#define STATUS_DONE   0x00000001u
#define STATUS_ERR    0x00000002u

/* volatile matters: without it the compiler will hoist the status read
   out of the polling loop and the function never returns.              */
static inline void  reg_write(u32 off, u32 v) { Xil_Out32(MYIP_BASE + off, v); }
static inline u32   reg_read (u32 off)        { return Xil_In32(MYIP_BASE + off); }

int myip_run(u32 a, u32 b, u32 timeout_iters)
{
    u32 status;

    reg_write(MYIP_CFG_A, a);
    reg_write(MYIP_CFG_B, b);
    reg_write(MYIP_CMD,   CMD_START);   /* self-clearing pulse in the PL */

    while (timeout_iters--) {
        status = reg_read(MYIP_STATUS);
        if (status & STATUS_ERR)  return -1;
        if (status & STATUS_DONE)  return 0;
    }
    return -2;                           /* never poll without a bound */
}

#include "xaxidma.h"
#include "xil_cache.h"

static XAxiDma dma;

/* ---- PL reads a buffer the CPU just filled -------------------------- */
int send_to_pl(u8 *buf, u32 len)
{
    int status;

    /* Push our dirty cache lines out to DDR FIRST. Skip this and the
       DMA reads whatever was in DDR before - often zeros, sometimes
       last frame's data, always confusing.                             */
    Xil_DCacheFlushRange((UINTPTR)buf, len);

    status = XAxiDma_SimpleTransfer(&dma, (UINTPTR)buf, len,
                                    XAXIDMA_DMA_TO_DEVICE);
    if (status != XST_SUCCESS) return status;

    while (XAxiDma_Busy(&dma, XAXIDMA_DMA_TO_DEVICE)) { }
    return XST_SUCCESS;
}

/* ---- CPU reads a buffer the PL just wrote --------------------------- */
int recv_from_pl(u8 *buf, u32 len)
{
    int status;

    status = XAxiDma_SimpleTransfer(&dma, (UINTPTR)buf, len,
                                    XAXIDMA_DEVICE_TO_DMA);
    if (status != XST_SUCCESS) return status;

    while (XAxiDma_Busy(&dma, XAXIDMA_DEVICE_TO_DMA)) { }

    /* Throw away any cached copies of these lines so the next load
       actually goes to DDR.                                            */
    Xil_DCacheInvalidateRange((UINTPTR)buf, len);
    return XST_SUCCESS;
}

// Level-sensitive interrupt: assert on completion, hold until the ISR
// clears it by writing 1 to the status bit. This is the shape the GIC
// expects for a peripheral with a status register.
always_ff @(posedge clk) begin
  if (!rstn) begin
    irq        <= 1'b0;
    done_latch <= 1'b0;
  end else begin
    if (engine_done)              done_latch <= 1'b1;   // set on event
    else if (clear_done_w1c)      done_latch <= 1'b0;   // cleared by SW

    irq <= done_latch && irq_enable;
  end
end

#include "xscugic.h"

static XScuGic gic;

/* The handler runs in interrupt context. Keep it short: clear the
   source, set a flag, return. Never block, never printf.              */
static void myip_isr(void *arg)
{
    u32 status = reg_read(MYIP_STATUS);

    if (status & STATUS_DONE) {
        reg_write(MYIP_STATUS, STATUS_DONE);   /* write-1-to-clear     */
        transfer_complete = 1;                  /* volatile global      */
    }
}

int irq_init(void)
{
    XScuGic_Config *cfg = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
    XScuGic_CfgInitialize(&gic, cfg, cfg->CpuBaseAddress);

    /* Priority 0xA0, trigger 0x3 = rising edge. Use 0x1 for level-high
       if your PL holds irq until software clears it.                  */
    XScuGic_SetPriorityTriggerType(&gic, XPAR_FABRIC_MYIP_IRQ_INTR,
                                   0xA0, 0x3);

    XScuGic_Connect(&gic, XPAR_FABRIC_MYIP_IRQ_INTR,
                    (Xil_ExceptionHandler)myip_isr, NULL);
    XScuGic_Enable(&gic, XPAR_FABRIC_MYIP_IRQ_INTR);

    Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
        (Xil_ExceptionHandler)XScuGic_InterruptHandler, &gic);
    Xil_ExceptionEnable();
    return XST_SUCCESS;
}