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4. Volume 02

2.1 Elaboration is not synthesis

Two entirely different transformations happen before you ever see a LUT, and conflating them is why "it elaborates fine but synthesis complains" feels arbitrary.

Elaboration resolves the language. Parameters are substituted, generate blocks are unrolled, for loops are flattened, module instances are bound, and the whole thing becomes a hierarchy of generic operators - RTL_ADD, RTL_MUX, RTL_REG, RTL_ROM. Nothing device-specific has happened yet. You can elaborate a design without even selecting a part.

Synthesis maps those generic operators onto the actual primitives in the device you chose. RTL_ADD becomes LUT2 plus CARRY4. RTL_REG becomes FDRE. RTL_ROM becomes either a RAMB36E1 or a pile of LUT6s depending on its size and shape. This step is where every decision from Volume 01 gets made on your behalf.

What synthesis is allowed to do to your code

Synthesis is an optimiser, and optimisers delete things. Four transformations surprise people regularly:

module sync_2ff (
  input  logic clk,       // destination clock
  input  logic d_async,   // from another domain - unrelated to clk
  output logic q_sync
);

  // ASYNC_REG does three things at once:
  //   1. forbids merging these two flops into one
  //   2. tells the placer to put them in the SAME slice (short route)
  //   3. tells simulation not to propagate X on a timing violation
  (* ASYNC_REG = "TRUE" *) logic meta_q;
  (* ASYNC_REG = "TRUE" *) logic sync_q;

  always_ff @(posedge clk) begin
    meta_q <= d_async;
    sync_q <= meta_q;
  end

  assign q_sync = sync_q;

endmodule

2.2 Attributes and directives: steering the tool

You cannot rewrite Vivado's optimiser, but you can constrain it. Two mechanisms exist, and they operate at different scopes: attributes are written into the RTL and attach to a specific object; directives are command-line switches that change the whole run's strategy.

The attributes worth memorising

// ---- fan-out control -------------------------------------------------
// A reset or enable feeding 4000 flops has enormous fanout. Replicating
// the driver costs a handful of flops and can be worth 2 ns of slack.
(* MAX_FANOUT = 64 *) logic rst_n_int;

// ---- memory style ----------------------------------------------------
// 32 entries x 8 bits: too small to justify a whole BRAM tile.
(* RAM_STYLE = "distributed" *) logic [7:0] lut_table [0:31];

// ---- shift register style -------------------------------------------
// A 64-deep delay line maps to two SRL32s (2 LUTs!) instead of 64 flops.
// "srl_reg" adds one real flop at the output for better clock-to-out.
(* SRL_STYLE = "srl_reg" *) logic [63:0] delay_line;

// ---- FSM encoding ----------------------------------------------------
// Vivado chooses automatically and is usually right. Override only when
// you have measured a reason to.
(* FSM_ENCODING = "one_hot" *) state_e state, next_state;

// ---- debug -----------------------------------------------------------
// MARK_DEBUG keeps the net alive AND lets you attach an ILA probe to it
// from the netlist, without editing RTL again. See Volume 07.
(* MARK_DEBUG = "TRUE" *) logic [7:0] fsm_trace;

Directives: whole-run strategy

Each implementation command takes a -directive. These are not knobs you tune randomly - each one trades runtime for a specific kind of quality, and there is a right order to try them in when you are 200 ps short.

# Baseline: fast, and what the GUI runs by default.
synth_design -directive default
place_design -directive default
route_design -directive default

# Short on setup slack? Push the placer harder before touching RTL.
place_design -directive ExtraTimingOpt
phys_opt_design -directive AggressiveExplore
route_design -directive AggressiveExplore

# Running out of area, not time?
synth_design -directive AreaOptimized_high

# Routing congestion (many "overlap" messages, long route times)?
place_design -directive AltSpreadLogic_high
route_design -directive AlternateCLBRouting

# Reproducing a customer's exact result? Pin the seed.
place_design -directive default -seed 7

2.3 Opt, place, phys_opt, route

Implementation takes the synthesised netlist and turns it into physical reality. Four commands do the work, and each has a strict contract about what it may modify.

phys_opt_design is the one worth understanding properly, because it is the only stage that can restructure logic with real placement information in hand. Before placement, the tool guesses that a net will be short. After placement it knows the driver is in clock region X0Y2 and one of its forty loads is in X3Y0. That knowledge unlocks fixes that were invisible earlier:

• Fanout replication - duplicate a driver and give each copy the loads physically near it. This is the single highest-value physical optimisation.
• Critical-cell placement - pull the endpoints of the worst path closer together, accepting a small penalty everywhere else.
• Register retiming - push a flop forwards or backwards across combinational logic to rebalance two adjacent stages.
• DSP and BRAM register absorption - pull a fabric flop into the DSP's PREG or the BRAM's output register, removing a routing hop entirely.

2.4 Reading the reports

Two reports decide whether you ship. Everything else is supporting evidence.

report_utilization

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs                 | 28451 |     0 |     53200 | 53.48 |
|   LUT as Logic             | 25103 |     0 |     53200 | 47.19 |
|   LUT as Memory            |  3348 |     0 |     17400 | 19.24 |
| Slice Registers            | 41120 |     0 |    106400 | 38.65 |
| Block RAM Tile             |  98.5 |     0 |       140 | 70.36 |
| DSPs                       |    44 |     0 |       220 | 20.00 |
| Bonded IOB                 |   112 |   112 |       200 | 56.00 |
| BUFGCTRL                   |     5 |     0 |        32 | 15.63 |
+----------------------------+-------+-------+-----------+-------+

The rows that actually predict trouble are not the ones people look at:

• Block RAM at 70% is far more dangerous than LUTs at 53%. BRAM tiles are in fixed columns; once they are scarce, the placer must stretch logic across the die to reach the remaining ones, and routing congestion follows.
• "LUT as Memory" is your distributed RAM and SRLs. High numbers here mean SLICEM sites are being consumed, which reduces packing freedom (see §1.3).
• Half-tiles. "98.5" block RAMs means some 36Kb tiles are split into 18Kb halves. Fine - but it also means you cannot assume 140 - 98 = 42 usable tiles remain.
• Run it with -hierarchical when a number surprises you. Per-module attribution turns "where did 8000 LUTs come from" into a two-minute question.

Anatomy of a timing path

Everything in static timing analysis reduces to one comparison: does the data arrive before it is required? The theory is in Volume 07 of the Verilog course; here is what Vivado's version of it looks like.

# The four commands that answer "why is my design failing timing", in order.

# 1. Is anything actually failing, and how badly?
report_timing_summary -delay_type min_max -max_paths 10 -file timing_sum.rpt

# 2. Show me the worst path with full detail.
report_timing -delay_type max -max_paths 1 -nworst 1 -significant_digits 3

# 3. Are my clocks what I think they are? (Catches the biggest failures.)
report_clocks
report_clock_interaction -delay_type min_max

# 4. Which nets have absurd fanout?
report_high_fanout_nets -timing -load_types -max_nets 20

2.5 Bitstream, configuration and the Tcl flow

write_bitstream serialises the routed design into the configuration bits that will be shifted into the device's SRAM at power-up. Two things about it matter in practice.

First, it runs design rule checks that nothing earlier runs. An unconnected I/O buffer, a missing CFGBVS setting, or a pin assigned to a bank whose voltage contradicts its I/O standard will all pass place-and-route and fail here - after the twenty minutes you just spent routing. Run report_drc after opt_design to catch these early.

Second, an FPGA's configuration is volatile. The bitstream lives in external flash and is loaded on every power-up:

Non-project mode: the flow you can put in git

A Vivado .xpr project is a directory of tool state that changes every time you open it, which makes it close to useless in version control. Non-project mode is a Tcl script that reads your sources, runs the flow and writes outputs - reproducible, diffable, and the way essentially every production team runs builds.

# ---------------------------------------------------------------------
# Non-project build. Run with:  vivado -mode batch -source build.tcl
# ---------------------------------------------------------------------
set part      xc7a100tcsg324-1
set top       system_top
set outdir    ./build

file mkdir $outdir

# ---- read sources (order does not matter; Vivado resolves it) --------
read_verilog -sv [glob ./rtl/*.sv]
read_xdc  ./constraints/timing.xdc
read_xdc  ./constraints/pins.xdc

# ---- synthesis -------------------------------------------------------
synth_design -top $top -part $part -directive default
write_checkpoint -force $outdir/post_synth.dcp
report_utilization -file $outdir/post_synth_util.rpt

# ---- implementation --------------------------------------------------
opt_design
report_drc -file $outdir/drc.rpt          ;# catch pin/bank errors EARLY

place_design
phys_opt_design -directive AggressiveExplore
write_checkpoint -force $outdir/post_place.dcp

route_design
write_checkpoint -force $outdir/post_route.dcp

# ---- sign-off --------------------------------------------------------
report_timing_summary -file $outdir/timing.rpt
report_utilization    -file $outdir/util.rpt

# Fail the build if timing did not close. Without this, CI will happily
# publish a bitstream that does not work.
set wns [get_property SLACK [get_timing_paths -delay_type max]]
if {$wns < 0} {
  puts "ERROR: setup timing failed, WNS = $wns ns"
  exit 1
}

write_bitstream -force $outdir/$top.bit
exit 0

Volume 02 recap