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4. Volume 06

6.1 Period, duty cycle and waveform

A clock is described by three numbers: its period, when it rises, and when it falls. The last two set the duty cycle, and any path that uses both edges of the clock lives or dies by it.

A timing tool knows a clock only by what it is told. In the constraint language the course meets in Volume 13, one line says it all:

create_clock -name clk -period 10 -waveform {0 5} [get_ports clk]

This says: a clock called clk, 10 ns long, rising at 0 and falling at 5, arriving on the port clk. The waveform gives the edge times within one period, and every later edge is a whole period on.

Why the duty cycle matters

A path from a rising-edge flip-flop to a falling-edge flip-flop gets only the time from the rise to the fall. That is the high part of the clock:

Take a rise-to-fall path needing 3.70 ns for clock-to-Q and logic, with a 0.12 ns setup time. At 50% duty its slack is 1.18 ns. Let the duty cycle slip to 40% and the slack falls to 0.18 ns. The period never changed.

6.2 Clock latency: source and network

Clock latency comes in two parts. Source latency is the time from where the clock is made to where the design's clock begins. Network latency is the time across the design's own clock tree.

For paths inside the design, the source part cancels

Both flip-flops of a register-to-register path get their clock from the same source. So the source latency appears on the arrival side and the required side alike, and drops out. Only the network latency to each flip-flop - and so the skew - is left.

For paths to and from the outside world, it is different

An input path starts at a flip-flop in another chip. That flip-flop shares the clock source, so the source latency still cancels. But it does not share our clock tree. So the network latency to our capture flip-flop is left over, and it helps: the capture edge arrives later.

An output path is the mirror image: our launch flip-flop's network latency makes the data leave later, and it hurts.

All at 5 ns. The input path has a 3.00 ns input delay and 1.20 ns of logic. The output path has 0.21 + 1.00 ns, and a 2.00 ns output delay. The source latency changed nothing anywhere. The network latency moved the input and output paths by exactly its own size.

6.3 Skew: positive, negative and useful

Skew is the difference in clock arrival between two flip-flops. It helps setup when the capture clock is later, and hurts hold by the same amount. Designers can even add it on purpose.

Local skew and global skew

Take four flip-flops, with clock latencies of 0.82, 0.85, 0.91 and 0.88 ns. Two numbers describe their skew:

Global skew describes the clock tree. Local skew is what a path actually feels. Only local skew enters a timing check, and it has a sign.

Positive and negative skew

1. Positive skew: the capture flip-flop gets the clock later. Setup gains; hold loses.
2. Negative skew: the capture flip-flop gets it earlier. Setup loses; hold gains.

Volume 05 drew the window of skew where both checks pass. Every pair of flip-flops has one.

Useful skew: lending time

Two stages in a row, on a 5 ns clock. Stage A, from FF1 to FF2, fails setup by 0.30 ns. Stage B, from FF2 to FF3, has 0.80 ns to spare. FF2 sits in the middle of both.

Delay FF2's clock by 0.40 ns. Stage A gets 0.40 ns more to reach FF2. Stage B loses 0.40 ns, because FF2 now launches later.

Both stages now pass setup. Stage A's hold slack dropped by 0.40 ns but is still comfortable; stage B's hold improved. This is useful skew, and clock tree tools use it on purpose.

6.4 Jitter and uncertainty

Jitter is the clock edge wandering from cycle to cycle. Nobody can remove it in the design, so a margin is taken for it - and for anything else not yet known - as clock uncertainty.

A clock comes from a PLL or an oscillator, and neither is perfect. Each edge lands a few picoseconds early or late compared with a perfect clock. From one cycle to the next the period is never quite the same.

Building the uncertainty

Clock uncertainty is a single number, but it is built from parts. Before the clock tree exists, it also has to stand in for skew nobody knows yet.

Two things to notice. After the tree is built, the skew estimate goes, because the real skew is now in the clock latencies. And hold carries no jitter at all: its launch and capture are the same edge, so that edge cannot differ from itself.

What it costs

At 5 ns, the Volume 04 logic has 1.63 ns of setup slack with the early uncertainty of 0.18 ns. With the later 0.08 ns it has 1.73 ns. Jitter matters more as clocks get faster: 50 ps of jitter is 5% of a 1 GHz cycle, but only 0.5% of a 100 MHz one.

6.5 Ideal versus propagated clocks

An ideal clock reaches every flip-flop at once; a propagated clock uses the real delays through the built tree. Early in a project you only have the first, and it is a guess. The second is the truth.

The clock tree is built by clock tree synthesis, after the cells have been placed. Until then there is no tree to measure. So the tool treats the clock as ideal, and leans on the uncertainty to cover the skew it cannot see.

# before clock tree synthesis: ideal clock, generous margin
set_clock_uncertainty -setup 0.18 [get_clocks clk]
set_clock_uncertainty -hold  0.13 [get_clocks clk]

# after clock tree synthesis: measure the real tree
set_propagated_clock [all_clocks]
set_clock_uncertainty -setup 0.08 [get_clocks clk]
set_clock_uncertainty -hold  0.03 [get_clocks clk]

The same two paths, both ways

The adder path looked worse with the ideal clock, because the generous margin was pessimistic for it. The short path looked better, because the guessed 0.10 ns of skew was smaller than the real 0.14 ns. Its hold violation only appeared once the real tree was measured.

What you learned

• A clock is described by its period and its waveform; the duty cycle sets the time for half-cycle paths.
• Source latency is shared, so it cancels; network latency matters wherever a path leaves the design.
• Global skew describes a clock tree; local skew, with its sign, is what a path feels.
• Useful skew lends setup time from one stage to the next, at a cost in hold.
• Jitter is cycle-to-cycle wander, covered by clock uncertainty, and it does not apply to hold.
• Before the clock tree, uncertainty also covers unknown skew; afterwards, the real latencies do.
• Ideal clocks are for planning; propagated clocks are for sign-off.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Duty cycle
• Source latency
• Network latency
• Useful skew
• Jitter
• PLL (phase-locked loop)
• Clock uncertainty
• Ideal clock
• Propagated clock
• Clock tree synthesis (CTS)

Practice

Interview corner

Volume 07 takes every clocking case in turn. It covers paths between rising and falling edges, divided and generated clocks, and clocks with awkward ratios. Then come clocks that have nothing to do with each other, and clocks that pass through multiplexers and gates.