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4. Volume 10

10.1 Input delay

An input delay describes the half of an input path that lies outside your design. It is built from the sending chip's datasheet and the board. It is how long after the clock edge the data leaves that chip, plus how long it takes to cross the board.

A timing tool knows everything inside your design and nothing outside it. For an input path, the data was launched by a flip-flop in another chip, on the same board clock, and spent time getting to your pin. You tell the tool how much.

From the datasheet to the constraint

The sending chip's datasheet gives its clock-to-out: at most 4.0 ns, at least 1.0 ns. The board trace takes between 0.5 and 0.8 ns.

set_input_delay -clock clk -max 4.80 [get_ports in_data]
set_input_delay -clock clk -min 1.50 [get_ports in_data]

Timing the path

Inside our design, the pad and logic take 1.20 ns (0.40 fastest). The clock tree reaches the capture flip-flop after 0.60 ns. Setup is 0.10 ns and hold is 0.05 ns, on a 10 ns clock.

So the most logic this input can go through inside our chip, on setup, is 10.00 + 0.60 - 0.10 - 4.80 = 5.70 ns.

10.2 Output delay

An output delay describes what the receiving chip needs after your pin. Its maximum is the trace plus the receiver's setup time. Its minimum is the trace less the receiver's hold time - and that is often negative.

Now the other direction. Our flip-flop launches data out of a pin, across the board, into another chip's flip-flop. That chip's datasheet gives its setup time, 2.0 ns, and hold time, 0.5 ns. The trace takes 0.4 to 0.7 ns.

The minimum is negative, and that is correct. Their hold time is longer than the shortest trace, so our data must stay put for a little after the clock edge: 0.10 ns.

Timing the path

Our clock tree reaches the launch flip-flop after 0.60 ns. Clock-to-Q is 0.30 ns (0.20 fastest), and the logic and output pad take 2.10 ns (0.90 fastest).

Notice that our own clock tree, 0.60 ns, is on the arrival side only. Volume 06 showed why: the other chip does not share our tree, so our clock latency makes our outputs late.

10.3 Virtual clocks

A virtual clock is a clock with no pin in the design. It stands for the other chip's clock, so input and output delays can be measured from the edge that really launched or captures the data.

So far the other chip ran on our clock, edge for edge. Suppose instead its clock rises 2 ns after ours, because it comes from a different buffer on the board. Our design has no pin carrying that clock - so we declare a virtual one.

create_clock -name vclk -period 10 -waveform {2 7}
set_input_delay -clock vclk -max 4.80 [get_ports in_data]
set_input_delay -clock vclk -min 1.50 [get_ports in_data]

Now the tool pairs the edges properly, using the rule from Volume 07:

The input really does have 2 ns less for setup, and 2 ns more margin for hold. Tying the delay to our own clock would have hidden both.

10.4 System-synchronous versus source-synchronous

When both chips share one board clock, the data's whole trip must fit in a cycle, and speed runs out quickly. Sending the clock along with the data makes the trip cancel - which is how every fast interface works.

System-synchronous: one clock for everyone

A system-synchronous interface is the one in 10.1: a single board clock drives both chips. Everything must fit inside one clock period:

1. the sender's clock-to-out: 4.00 ns
2. the board trace: 0.80 ns
3. the skew between the board clock at the two chips: 0.50 ns
4. our input path and setup time: 1.30 ns

That adds up to 6.60 ns, so this interface can run no faster than 151.5 MHz. And every term is fixed by the board and the other chip. There is little you can do inside your design.

Source-synchronous: send the clock with the data

In a source-synchronous interface, the sending chip forwards its own clock on a pin next to the data. The clock and the data leave together and travel matched traces.

So the clock-to-out and the trace delay affect both equally, and cancel. What is left is only the skew between data and clock - the small differences between the two traces and the two output buffers.

Take a skew of up to 0.30 ns either way, and a receiver setup and hold of 0.20 ns each. Then one bit needs 0.30 + 0.30 + 0.20 + 0.20 = 1.00 ns. That is 1000 Mb/s per pin, against about 151 for the system-synchronous version.

10.5 DDR interfaces

A DDR interface sends data on both clock edges, so each bit gets half a period. The receiver captures each bit with a strobe whose edges sit in the middle of the bit, leaving equal margin on both sides.

With the strobe centred, each side of the bit gets half of it. From that half come the skew and the receiver's setup time (or hold time, on the other side). With a skew of 0.30 ns and a setup of 0.20 ns:

At 500 MHz the margin reaches zero: that is the same 1000 Mb/s per pin the source-synchronous sum in 10.4 found. Beyond it, the skew must shrink. Real DDR memories train their strobe delays at power-on, bit by bit, for exactly this reason.

Constraining both edges

DDR inputs need input delays for the rising and the falling edge. In SDC that is done with -clock_fall and -add_delay, so the second pair of numbers is added rather than replacing the first.

Here dqs is the strobe as it arrives at the pins, lined up with the data edges. So the data may change up to 0.30 ns either side of each strobe edge. The receiver then delays the strobe by a quarter period inside the chip, which centres it as in the figure.

set_input_delay -clock dqs -max 0.30 [get_ports dq*]
set_input_delay -clock dqs -min -0.30 [get_ports dq*]
set_input_delay -clock dqs -max 0.30 [get_ports dq*] -clock_fall -add_delay
set_input_delay -clock dqs -min -0.30 [get_ports dq*] -clock_fall -add_delay

What you learned

• Input delay = the sender's clock-to-out plus the board trace: -max for setup, -min for hold.
• Output delay = the trace plus the receiver's setup (-max), or the trace less its hold (-min).
• A negative minimum output delay is normal, and must not be left out.
• Our own clock tree latency helps inputs and hurts outputs.
• A virtual clock describes an outside chip's clock so its edges are paired correctly.
• System-synchronous interfaces run out of speed; source-synchronous ones cancel the trace delay.
• DDR halves the time per bit, and centres a strobe in each bit to share the margin.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Input delay
• Clock-to-out
• Output delay
• Virtual clock
• System-synchronous
• Source-synchronous
• DDR (double data rate)
• Strobe

Practice

Interview corner

Volume 11 turns to variation. No two chips, and no two gates on one chip, have quite the same delay - so how does a timing tool make sure a design works on all of them?