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3. Static Timing Analysis from Zero
4. Volume 05

5.1 Hold arrival and required time

A hold check asks whether new data can arrive too soon. It takes the earliest the data can reach the capture flip-flop, and compares it with how long the old value must be held. Both are counted from the same clock edge.

At every clock edge two things happen at once. The launch flip-flop sends out new data, and the capture flip-flop stores the old data sitting at its input. If the new data reaches the capture flip-flop before it has finished storing, the old value is spoiled.

So this time the danger is a fast path. Everything is measured with the fastest delays the library allows, because the question is how early the data could possibly be.

The short path

This volume uses a short path on the same 200 MHz clock as Volume 04: one buffer between two flip-flops, with the capture clock arriving a little late.

Hold arrival: the earliest the data can get there

Hold required: how long the old value must be left alone

5.2 Hold slack

Hold slack is the arrival time minus the required time - the other way round from setup. Negative hold slack means the new data got there too soon.

For the short path:

It fails, by 10 picoseconds.

The same sum on one line

Let the source latency cancel, and write skew as the capture clock arrival minus the launch clock arrival (0.97 - 0.83 = +0.14 ns):

0.15 + 0.05 - 0.04 - 0.14 - 0.03 = -0.01 ns. Compare it with the setup line from Volume 04:

Look at the skew row. A late capture clock gives setup more time and hold less. It is the same 0.14 ns, pulling the two checks in opposite directions.

A long path is safe from hold

The adder path from Volume 04 has fast numbers too: its logic takes at least 1.14 ns. Its hold arrival is 2.14 ns and its hold required time is 0.95 ns, giving a hold slack of +1.19 ns. Long paths almost never fail hold. The dangerous ones are short: a buffer, a wire, or nothing at all.

5.3 Why hold ignores the clock period

A hold check compares a clock edge with itself, so the clock period cancels out. A hold violation is exactly the same at any frequency - which is why it is the more dangerous of the two.

Volume 01 showed this with one path. Here it is again with the short path, checked at five clock speeds:

The setup slack follows the period exactly. The hold slack does not move at all.

Why the period drops out

1. Setup compares the launch edge with the next edge, one period later. The period is the gap between them, so it sits in the sum.
2. Hold compares the launch edge with the capture that happens at that same edge. There is no gap between them to measure.
3. So hold depends only on how fast the path is and how the clock tree is balanced - both fixed once the chip is built.

5.4 Ten worked hold problems

Nine hold problems, then one that puts setup and hold side by side. Use the one-line formula: slack = clock-to-Q + logic - hold - skew - uncertainty, all with the fastest delays.

Problem 10: setup and hold together

One path, both checks. T = 2.00 ns. Clock-to-Q 0.10 ns slowest and 0.08 ns fastest. Logic 1.70 ns slowest and 0.05 ns fastest. Setup 0.06 ns, hold 0.05 ns, and skew +0.10 ns.

1. Setup: 2.00 + 0.10 - 0.10 - 1.70 - 0.06 = +0.24 ns, met.
2. Hold: 0.08 + 0.05 - 0.05 - 0.10 = -0.02 ns, violated.
3. The same skew that helps setup is what breaks hold.

So what skew would work? Setup needs 0.14 + skew to stay above zero, so skew must be at least -0.14 ns. Hold needs 0.08 - skew to stay above zero, so skew must be at most +0.08 ns.

5.5 Reading a hold report

A hold report has the same shape as a setup report. Only three things differ: it says "min", the capture edge is the launch edge, and the last lines subtract the other way.

Startpoint: u_ff3
Endpoint:   u_ff4
Path Group: clk
Path Type:  min

  Point                                              Incr     Path
  ----------------------------------------------------------------
  clock clk (rise edge)                              0.00     0.00
  clock source latency                               0.50     0.50
  clock network delay (propagated)                   0.33     0.83
  u_ff3/CK                                           0.00     0.83
  u_ff3/Q (clock-to-Q)                               0.15     0.98
  u5/Y (BUF_X1)                                      0.05     1.03
  u_ff4/D                                            0.00     1.03
  data arrival time                                           1.03

  clock clk (rise edge)                              0.00     0.00
  clock source latency                               0.50     0.50
  clock network delay (propagated)                   0.47     0.97
  u_ff4/CK                                           0.00     0.97
  clock uncertainty                                  0.03     1.00
  library hold time                                  0.04     1.04
  data required time                                          1.04
  ----------------------------------------------------------------
  data arrival time                                           1.03
  data required time                                         -1.04
  ----------------------------------------------------------------
  slack (VIOLATED)                                           -0.01

The three differences from a setup report

1. "Path Type: min". The fastest delays were used throughout. A setup report says "max".
2. The second clock edge is at 0.00, not at 5.00. Same edge at both ends. No period appears anywhere.
3. The uncertainty and the hold time are added, not subtracted. And the last lines take the required time away from the arrival, the reverse of setup.

Reading it for a fix

Look at the clock lines first. The clock network delay is 0.33 ns to u_ff3 but 0.47 ns to u_ff4: a skew of 0.14 ns. The whole path's data delay is only 0.20 ns. So there are two ways to fix it:

Both fixes clear the violation, and both cost a little setup slack. With 4.6 ns of setup slack to spare, that costs nothing that matters here.

What you learned

• Hold asks whether new data can arrive before the old capture is finished, at the same clock edge.
• Hold arrival uses the fastest delays; hold required adds the capture clock, uncertainty and hold time.
• Hold slack = clock-to-Q + logic - hold - skew - uncertainty, and no clock period appears.
• Long paths fail setup; short paths fail hold.
• Skew helps one check and hurts the other, leaving a window of skew where both pass.
• A hold violation is fixed with delay in the data path or a better-balanced clock tree, never by slowing the clock.
• A hold report says "min", uses the same edge twice, and subtracts the required time from the arrival.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Delay cell

Practice

Interview corner

Volume 06 turns to the clock itself. It covers the waveform and duty cycle, where latency comes from, skew in all its forms, jitter, and the difference between an ideal clock and a real one.