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3. Static Timing Analysis from Zero
4. Volume 07

7.1 Half-cycle paths, rise to fall

One rule chooses the edges for every check in this volume. For setup, take each launch edge and find the first capture edge after it; the closest such pair is checked. For hold, check one capture edge earlier than that.

Volume 03 met the rule in its simplest form. Here it meets a half-cycle path: launched on a rising edge and captured on a falling one, or the other way round.

Take one path on a 10 ns, 50% clock. Its clock-to-Q is 0.30 ns (0.20 fastest) and its logic 3.40 ns (0.50 fastest). Setup is 0.12 ns and hold 0.05 ns. Launch and capture it on different edges:

The half-cycle paths lose 5 ns of setup, because they get half a period. But look at hold. The capture edge one period before the setup capture comes half a period before the launch. So the data has a whole half-period to spare, and hold slack jumps from 0.65 to 5.65 ns.

7.2 Inverted and negative-edge clocks

A flip-flop that acts on the falling edge, and a flip-flop whose clock passes through an inverter, are the same thing to a timing tool: both capture on the fall. The inverter just adds its delay to that clock's latency.

There are two ways to build a flip-flop that acts on the falling edge. Use a cell made for it, or put an inverter in front of an ordinary rising-edge flip-flop's clock pin. The tool traces the clock through the inverter, sees the edge flip, and times the path exactly like a falling-edge capture.

The only difference is the inverter's own delay, which arrives on the capture side. For the rise-to-fall path above, an inverter of 0.06 ns in the capture clock gives:

The later capture clock helps setup and hurts hold by the inverter's 0.06 ns, as any skew would.

7.3 Generated and divided clocks

A generated clock is made inside the design from another clock, such as a divide-by-2 from a flip-flop. Declaring it as generated tells the tool how its edges line up with the master, and adds the generating logic's delay to its latency.

A flip-flop whose output feeds back through an inverter toggles on every rising clock edge, making a clock at half the frequency. From a 5 ns master, the result is a 10 ns clock.

create_clock -name clk -period 5 [get_ports clk]
create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins u_div/Q]

Which edges get compared

Both directions get one period of the fast clock. From fast to slow, the fast clock's second launch edge is the one closest to the slow capture. From slow to fast, the fast clock captures one of its own periods after the slow launch.

Why the declaration matters

The divider flip-flop takes 0.25 ns to produce each edge of clk_div2. Declared as a generated clock, that 0.25 ns becomes part of clk_div2's latency. Declared as an unrelated clock with its own create_clock, it is lost.

One direction looks 0.25 ns worse than the truth; the other looks 0.25 ns better. The optimistic one is the dangerous one: a chip can pass timing on paper and fail on the bench.

7.4 Related clocks with odd ratios

When two clocks come from the same source but at an awkward ratio, their edges only line up now and then. The tightest setup check between them is the greatest common divisor of their periods - which can be far shorter than either period.

Take a 125 MHz clock (8 ns) and a 100 MHz clock (10 ns), both from one PLL, with edges lined up at time zero. They line up again only every 40 ns. In between, the launch and capture edges fall in every possible relationship:

The tool checks the worst: 2 ns. A path that would be easy on either clock alone has to fit in 2 ns when it crosses between them.

The rule

For two clocks whose edges line up at zero, the tightest setup pair is the greatest common divisor (GCD) of their periods. The engine behind this course checks every case in the table against that rule:

In every case the hold check lands at 0: the edges that line up at time zero give the usual same-edge hold check.

Take a 2.30 ns path from the 125 MHz clock to the 100 MHz clock, with 0.20 ns clock-to-Q and 0.10 ns setup. Its slack is 2.00 - 0.20 - 2.30 - 0.10 = -0.60 ns. It fails, although either clock alone gives 8 ns or more.

7.5 Asynchronous clocks and clock groups

Clocks from unrelated sources have no fixed relationship at all, so any timing check between them is meaningless. They are declared as separate clock groups, and the crossings are made safe by design instead.

Suppose one clock is 10 ns and the other is 7.3 ns, from two different crystals. Use the GCD rule anyway and see what happens:

The tool would demand that paths between them fit in a few tens of picoseconds. And even that is fiction: two free-running crystals drift, so the edges do not really repeat at all. Given enough time, some edge pair will land as close together as you like.

set_clock_groups -asynchronous -group [get_clocks clk_a] -group [get_clocks clk_b]

This line says: do not time any path between these two groups. The tool stops reporting absurd violations. But it has not made the crossing safe - it has only stopped checking it.

7.6 Clock muxes and clock-gating checks

Clocks that pass through logic need special care. A clock multiplexer carries two clocks that never run at once, so they must not be timed against each other. A clock gate needs its own clock-gating check on its enable.

Clock multiplexers

A clock mux lets the chip run the same logic from clkA (10 ns) or clkB (8 ns). Downstream, the tool sees both clocks arriving at every flip-flop. Left alone, it times paths launched by clkA and captured by clkB - which cannot happen, since only one is ever selected. It would find the 2 ns GCD from sub-module 7.4 and report violations that do not exist.

set_clock_groups -physically_exclusive -group [get_clocks clkA] -group [get_clocks clkB]

Clock gating

Clock gating saves power by stopping the clock to idle flip-flops. The simplest gate is an AND gate: gated clock = clk AND enable. But the enable must not change while the clock is high, or the output pulse is chopped - a glitch on a clock, which is a disaster.

So the tool checks the enable against the clock at the gate, like a tiny setup and hold check:

1. Gating setup: the enable must be settled before the clock rises.
2. Gating hold: for an AND gate, the enable must not change until the clock has fallen again.

On a 10 ns clock, with the enable coming from 0.20 ns of clock-to-Q and 0.60 ns of logic:

The fix is to change the enable only while the clock is low. Libraries provide an integrated clock gate. It is a latch that holds the enable steady while the clock is high, built together with the AND gate so the timing is right by construction.

What you learned

• Setup takes the closest launch-to-capture pair; hold checks one capture edge earlier.
• Half-cycle paths get half a period for setup, and half a period of extra hold margin.
• An inverted clock is a falling-edge capture, plus the inverter's delay.
• Generated clocks must be declared as generated, or their latency and phase are lost.
• Between related clocks, the tightest setup check is the GCD of their periods.
• Unrelated clocks go in separate clock groups, and their crossings need synchronisers.
• Clock muxes need exclusive clock groups; clock gates need gating checks and proper gate cells.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Half-cycle path
• Generated clock
• Clock groups
• Metastability
• Synchroniser
• Clock multiplexer
• Clock-gating check
• Glitch
• Integrated clock gate (ICG)

Practice

Interview corner

Volume 08 is about paths that should not be timed the normal way. It covers false paths, multicycle paths, max and min delays, and constant signals - and the damage each one does when it is wrong.