Latches and Time Borrowing
Every path so far has ended at a flip-flop: a hard wall that only opens at one instant. A latch is different. It stays open for part of the cycle, so data that is a little late can still get through, borrowing the time from whatever comes next. This volume shows how latches are timed, how much they can borrow, and how whole pipelines use that to share time between uneven stages.
- How a latch behaves differently from a flip-flop, on a waveform
- Where a latch's setup and hold checks are made
- How time borrowing works, how much a latch can lend, and who repays it
- How a two-phase latch pipeline shares time between uneven stages
- What a pulsed latch is, and why its danger is hold
9.1 How a latch differs from a flip-flop
A flip-flop acts at one instant, the clock edge. A latch is level-sensitive: while its clock is at the active level, its output simply follows its input. It is a door that stays open, not a camera shutter.
Feed the same data into a flip-flop and into a latch that is open while the clock is high. The difference shows at once.
Read cycle 2. D rises part-way through the high phase. The latch's output rises with it, straight away. The flip-flop does not notice at all, because no edge happened.
| Flip-flop | Latch | |
|---|---|---|
| Acts on | The clock edge | The clock level |
| Passes a change during the cycle? | Never | Yes, while it is open |
| Setup and hold checked against | The capturing edge | The closing edge |
| Can a late path borrow time? | No | Yes |
Latches are not a mistake in themselves. An accidental latch in RTL is a bug, because nobody planned its timing. A latch put there on purpose, and timed properly, is a powerful tool.
Thinking a latch is just a cheaper flip-flop. It behaves differently in time: anything arriving while it is open goes straight through. Timing a latch as if it were a flip-flop gets both setup and hold wrong.
A latch is open while the clock is high. Its input changes in the middle of the high phase. What does its output do?
Show the answer
Answer: C. While the latch is open it is transparent: the output follows the input, after a short D-to-Q delay. It only holds its value once the clock goes low.
9.2 Latch setup and hold
A latch's setup and hold are both checked against its closing edge. Data may arrive any time before the latch closes, less the setup time - including after it has opened.
Take a latch that opens at 10 ns and closes at 15 ns, with a setup time of 0.10 ns and a hold time of 0.05 ns.
| Check | Measured from | Deadline |
|---|---|---|
| Latch setup | The closing edge at 15 ns | Data steady by 14.90 ns |
| Latch hold | The closing edge at 15 ns | Data steady until 15.05 ns |
| A flip-flop at 10 ns, for comparison | The capturing edge at 10 ns | Data steady by 9.90 ns |
The latch gives the data until 14.90 ns. A flip-flop at the same place would have wanted it by 9.90 ns. That 5 ns is the open window, and it is where time borrowing comes from.
Setup is against the closing edge. Everything between the opening edge and the closing edge is time the latch can lend.
Checking a latch's hold against its opening edge. The latch keeps accepting data until it closes, so the value it finally holds is the one present at the closing edge. Hold protects that value, so it is measured from the closing edge too.
A latch opens at 20 ns and closes at 24 ns. Its setup time is 0.08 ns. By when must the data be steady?
Show the answer
Answer: D. Setup is measured against the closing edge: 24.00 - 0.08 = 23.92 ns. The opening edge at 20 ns is not a deadline - arriving after it is allowed.
9.3 Time borrowing
When data reaches a latch after it has opened, the latch passes it straight on. The late stage has used time belonging to the next stage: time borrowing. The loan is repaid by the next stage having less time.
A flip-flop launches at 0 ns. Its path ends at a latch open from 10 to 15 ns, with a setup time of 0.10 ns. The latch's D-to-Q delay is 0.15 ns, and its clock-to-Q from the opening edge is 0.20 ns.
| Data arrives at | Borrowed | Latch slack | Data leaves at |
|---|---|---|---|
| 9.20 ns | 0.00 ns | 5.70 ns | 10.20 ns (waits for the opening edge) |
| 11.80 ns | 1.80 ns | 3.10 ns | 11.95 ns |
| 14.60 ns | 4.60 ns | 0.30 ns | 14.75 ns |
| 15.20 ns | 4.90 ns (the most it can) | -0.30 ns | too late |
Latch slack is measured to the closing edge less setup: how much later the data could still have come. At 15.20 ns the data has missed the latch altogether. That is a real violation.
How much can be borrowed?
At most the time the latch is open, less its setup time: 5.00 - 0.10 = 4.90 ns. Past that, there is nothing left to borrow.
Who pays it back
Take the 11.80 ns arrival. It borrows 1.80 ns, and the data leaves the latch at 11.95 ns instead of 10.20 ns. The next stage has 6.90 ns of logic and ends at a flip-flop at 20 ns:
- It starts at 11.95 ns, and arrives at 11.95 + 6.90 = 18.85 ns.
- The flip-flop needs it by 20 - 0.10 = 19.90 ns.
- Slack: +1.05 ns. The loan is repaid, and both stages pass.
Put a flip-flop at 10 ns instead of the latch, and the first stage fails by -1.90 ns, while the second has 2.70 ns to spare. Same total logic. The latch simply let the two stages share their time.
Time borrowing does not create time. It moves time from a stage that has spare to a stage that needs it. The two must be next to each other, and the loan must fit in the latch's open window.
Reading a positive latch slack as "this stage is fine" without looking at the next one. A stage that borrows 4 ns passes its own check easily, and hands the problem to the next stage. Always read a latch path together with the path after it.
Data reaches a latch that is open from 10 to 15 ns (setup 0.10 ns) at 12.40 ns. How much has it borrowed, and what is the latch slack?
Show the answer
Answer: A. It arrived 2.40 ns after the latch opened, so it borrowed 2.40 ns. It could have arrived as late as 14.90 ns, so the latch slack is 14.90 - 12.40 = 2.50 ns. Arriving after the opening edge is not a failure; that is what latches are for.
9.4 Latch-based design examples
A pipeline of latches that open on alternate clock phases lets each stage borrow from the next. Uneven stages that would fail with flip-flops can pass, as long as the total fits.
Here is a three-stage path on a 10 ns clock. It starts at a flip-flop at 0 ns (clock-to-Q 0.30 ns). Latch L1 is open while the clock is low, from 5 to 10 ns. Latch L2 is open while it is high, from 10 to 15 ns. The path ends at a flip-flop at 20 ns.
| Stage | Logic | Ends at | Arrives | Borrowed | Slack | Leaves |
|---|---|---|---|---|---|---|
| 1 | 6.20 ns | L1, open 5 to 10 | 6.50 ns | 1.50 ns | 3.40 ns | 6.65 ns |
| 2 | 4.10 ns | L2, open 10 to 15 | 10.75 ns | 0.75 ns | 4.15 ns | 10.90 ns |
| 3 | 8.60 ns | flip-flop at 20 | 19.50 ns | - | 0.40 ns | - |
Now replace both latches with flip-flops at the same places, 5 ns and 10 ns:
| Stage | Slack with flip-flops |
|---|---|
| 1 | -1.60 ns: fails |
| 2 | 0.50 ns |
| 3 | 1.00 ns |
With flip-flops, stage 1 fails on its own, and the spare time in stages 2 and 3 cannot help it. With latches, stage 1 borrows, stage 2 borrows a little less, and everything passes. The 18.90 ns of logic fits the 20 ns because the latches let it be shared unevenly.
Latch-based design is how high-speed processors balance pipelines whose stages cannot be made equal. The price is harder timing analysis, and harder testing - which is why most designs use flip-flops.
Assuming borrowing can go on forever. Make stage 1 take 7.00 ns instead of 6.20 ns and it still passes its own latch. But the lateness is passed down the line, and stage 3 now fails by 0.40 ns. Borrowing moves a deficit along, and the last stage has to absorb it.
In the pipeline above, stage 1 grows from 6.20 ns to 7.00 ns. Which stage fails?
Show the answer
Answer: B. Stage 1 arrives at L1 later but still before it closes, so it borrows more and passes. That extra lateness flows through L1 and L2 to the end. Stage 3 reaches the flip-flop 0.80 ns later than before, and its slack drops from +0.40 to -0.40 ns.
9.5 Pulsed latches in brief
A pulsed latch is opened for only a tiny pulse after each clock edge. It works almost like a flip-flop, with a little borrowing. Its danger is hold, because the latch stays open for the whole pulse.
A flip-flop is really two latches back to back. A pulsed latch is just one, opened by a short pulse generated from each rising clock edge. It is smaller and faster than a flip-flop.
Take a pulse 0.15 ns wide, with a latch setup time of 0.02 ns and a hold time of 0.03 ns:
| Check | Relative to the rising edge |
|---|---|
| Setup: steady before the pulse ends, less setup | by 0.13 ns after the edge |
| Hold: steady until the pulse ends, plus hold | until 0.18 ns after the edge |
The setup side is generous: data may even arrive a little after the edge. The hold side is the problem. New data must not arrive within 0.18 ns of the edge, or it slips through the still-open latch.
| Fastest data arrives after the edge | Hold slack |
|---|---|
| 0.10 ns | -0.08 ns |
| 0.25 ns | +0.07 ns |
So designs using pulsed latches need many more delay cells on their short paths. That hold cost is the main reason they are used only where speed matters most.
Why is hold harder for a pulsed latch than for a flip-flop?
Show the answer
Answer: C. A flip-flop closes its door at the edge. A pulsed latch keeps it open for the width of the pulse. So the hold requirement is measured from the end of the pulse: 0.15 + 0.03 = 0.18 ns after the edge.
What you learned
- A latch is level-sensitive: while open, its output follows its input.
- Latch setup and hold are checked against the closing edge, not the opening one.
- Data arriving after the latch opens passes straight through, borrowing time from the next stage.
- A latch can lend at most its open time less its setup time.
- Latch pipelines let uneven stages share time; the lateness still has to be absorbed at the end.
- A pulsed latch behaves like a flip-flop with a little borrowing and a much harder hold check.
Key words from this volume
Every word below has a plain-English entry in the glossary.
Practice
The most a latch can lend
A clock of 8 ns has a 40% duty cycle. A latch is open while it is high, from 8 ns until 11.20 ns, with a 0.10 ns setup time. How much time can it lend? And how much does data arriving at 9.00 ns borrow?
Show the solution
The latch is open for 40% of 8 ns, which is 3.20 ns. Less its setup time, it can lend at most 3.20 - 0.10 = 3.10 ns.
Data arriving at 9.00 ns came 1.00 ns after the latch opened, so it borrows 1.00 ns.
Two arrivals
A latch is open from 10 to 15 ns, with a 0.10 ns setup time. Data arrives at 13.10 ns. How much has it borrowed, what is the latch slack, and what must you check next?
Show the solution
It borrowed 13.10 - 10.00 = 3.10 ns. Latch slack is 14.90 - 13.10 = 1.80 ns.
Next, check the stage after the latch. It starts 3.10 ns later than it would have with an on-time arrival, and it must still meet its own deadline.
Interview corner
Explain time borrowing
"What is time borrowing, and where does the borrowed time come from?"
Show the solution
"A transparent latch passes data as soon as it arrives, while it is open. Suppose a path arrives after the latch opens but before it closes. The latch does not make it wait - it forwards it at once, and the path has used some of the open window. That time comes out of the next stage, which starts later than it would if the data had arrived before the opening edge.
A timing tool checks latch setup against the closing edge, records how much was borrowed, and adds it to the start of the next stage. The most a latch can lend is its open time less its setup time."
Why not use latches everywhere?
"If latches can balance uneven stages, why do most designs use flip-flops?"
Show the solution
"Because flip-flops make every stage independent, which keeps timing analysis, closure and test simpler. With latches a late stage pushes its problem downstream, so paths have to be analysed in chains. Hold is harder, because data can race through transparent latches, and scan test is more complicated. Latches are worth it where the last few percent of speed matters, such as in processor pipelines, and in clock-gating cells, where one latch prevents glitches."
Volume 10 leaves the chip: how signals arriving from and leaving to other chips are constrained, including virtual clocks, source-synchronous interfaces and DDR.