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9.1 ROM and RAM

A memory is a large table of words. An address picks one word, and the memory reads or writes it. A ROM holds fixed contents; a RAM can be written as well as read, but forgets everything when the power goes off.

Words and addresses

A memory holds 2^k words of m bits each. It needs k address lines to choose a word, and m data lines to carry it:

In memory sizes, 1K means 1024 - that is, 2¹⁰ - and 1M means 2²⁰.

A ROM is a truth table

A ROM gives the same data for the same address every time, so it is just a truth table in hardware. Here is an 8-word ROM that turns a binary number into its Gray code from Volume 01:

Inside, a ROM is a decoder and a set of OR gates - exactly the "any function from a decoder" trick of Volume 05. The decoder turns the address into one active row, and each data bit ORs together the rows where it is 1:

data bit 1 = Y2 + Y3 + Y4 + Y5 of a 3-to-8 decoder: True

In a real ROM chip, the OR connections are made when the chip is built (mask ROM), or programmed afterwards with electricity. Some can be programmed once only; others can be erased and programmed again, as in the flash memory that holds a microcontroller's program.

RAM

RAM can be written as well as read. A write-enable input says which: with it active, the data lines are stored at the addressed word. There are two main kinds:

1. Static RAM (SRAM) stores each bit in a latch, like Volume 07's. It is fast, but takes six transistors per bit.
2. Dynamic RAM (DRAM) stores each bit as charge on a tiny capacitor, with one transistor. It is dense and cheap, but the charge leaks away, so every bit must be read and rewritten - refreshed - every few hundredths of a second.

Both are volatile: without power they forget everything. ROM and flash keep their contents.

Building a bigger memory from small chips

Exam questions love this. Build a 4K x 8 memory from 1K x 4 chips. Two chips side by side make 8-bit words, and four such rows make 4K words:

chips: (4K / 1K) x (8 / 4) = 4 x 2 = 8
address lines: 12 in all; 10 go to every chip, 2 go to a 2-to-4 decoder that picks a row of chips

The top two address bits go into a decoder, and each decoder output enables one row of chips. So each row answers a quarter of the addresses:

9.2 Programmable logic

Programmable logic is a chip whose logic function you set after it is made. A PLA or a PAL is an AND array feeding an OR array. An FPGA is built from small memories called look-up tables, each able to be any function of its inputs.

PLA and PAL

Every function can be written as a sum of products (Volume 03). So a chip with a row of AND gates feeding a row of OR gates can make any function - if you can choose the connections. A PLA lets you program both arrays. A PAL programs only the AND array; its OR connections are fixed, which makes it smaller and faster, at the cost of a fixed number of product terms per output.

Look-up tables and FPGAs

A look-up table is a tiny ROM. With k inputs it stores 2^k bits - one output for every input pattern - so it can be any function of its k inputs at all:

An FPGA is a large grid of such look-up tables, each paired with a flip-flop, joined by programmable wiring. Load a different pattern of bits, and the same chip becomes a different circuit. The FPGA course covers them in depth.

9.3 Digital to analogue: the DAC

A DAC, digital-to-analogue converter, turns a number into a voltage in proportion to it. The R-2R ladder does it with resistors of just two values: the output is Vref times the number, divided by 2ⁿ.

A microcontroller that plays a sound, or sets a motor's speed, must turn numbers into voltages. The simplest idea gives each bit its own resistor, weighted 1, 2, 4, 8 and so on, but those values are hard to make accurately. The R-2R ladder uses only two values, R and 2R:

The simulator solved this network exactly, with Kirchhoff's current law at every node, for all 16 input numbers:

Vout = Vref x D / 16 on all 16 codes, exactly: True

Resolution

One step of the input changes the output by Vref / 2ⁿ. That step is the DAC's resolution. The largest output is one step short of Vref:

4 bits, Vref 5.0 V: one step = 312.50 mV; full scale = 4.6875 V
8 bits, Vref 5.0 V: one step = 19.53 mV; full scale = 4.9805 V
10 bits, Vref 3.3 V: one step = 3.22 mV; full scale = 3.2968 V
12 bits, Vref 3.3 V: one step = 0.81 mV; full scale = 3.2992 V

Every extra bit halves the step.

9.4 Analogue to digital: the ADC

An ADC, analogue-to-digital converter, turns a voltage into a number. A flash ADC compares the input with every level at once; a successive-approximation ADC finds the number one bit at a time, with a DAC and a single comparator.

Successive approximation

A successive-approximation ADC plays "higher or lower". It sets the top bit, uses a DAC to make that number's voltage, and asks a comparator whether the input is higher. If it is, the bit stays; if not, it is cleared. Then it moves to the next bit. Here it measures 3.30 V with 8 bits and Vref = 5 V:

try 10000000 = 2.5000 V: input is higher, so bit 7 = 1
try 11000000 = 3.7500 V: input is lower, so bit 6 = 0
try 10100000 = 3.1250 V: input is higher, so bit 5 = 1
try 10110000 = 3.4375 V: input is lower, so bit 4 = 0
try 10101000 = 3.2813 V: input is higher, so bit 3 = 1
try 10101100 = 3.3594 V: input is lower, so bit 2 = 0
try 10101010 = 3.3203 V: input is lower, so bit 1 = 0
try 10101001 = 3.3008 V: input is lower, so bit 0 = 0
result: 10101000 = 168, which stands for 3.2813 V (the input is 0.0188 V above it)

Eight bits take eight steps, whatever the input. The answer is the input rounded down to a whole number of steps, and the part left over - here 0.0188 V - is the quantisation error. It is always less than one step.

Faster and slower

Flash ADCs compare the input with every level at once, using one comparator per level. That is as fast as possible, but the comparators double with every bit:

A counting ADC simply counts up until its DAC passes the input: one comparator, but up to 255 steps. Successive approximation sits in the middle, which is why most microcontroller ADCs use it.

9.5 Logic families: TTL and CMOS

A logic family is a way of building gates from transistors. TTL and CMOS differ in their voltage levels, how many inputs one output can drive, and how much power they use. Noise margins say how much noise each can stand.

Every gate on every chip is built from transistors, and there is more than one way to do it. The 7400 chips of Volume 02 were first made in TTL, transistor-transistor logic, built from bipolar transistors. Almost everything today is CMOS, built from pairs of complementary MOS transistors.

Noise margins

Volume 00 said a chip reads a voltage by comparing it with thresholds. A family's datasheet gives four numbers: the worst output voltages it promises (VOH for a 1, VOL for a 0) and the worst input voltages it accepts (VIH, VIL). The gaps between them are the noise margins: how much noise a signal can pick up between one gate and the next and still be read right.

NMH = VOH - VIH and NML = VIL - VOL. The TTL figures are the classic ones for the standard 7400 family; the CMOS row is an example for a 5 V CMOS chip with a light load. Always take real values from the datasheet of the part you use.

Fan-out

Fan-out is how many inputs one output can drive. In TTL each input draws current, so the output can only feed a limited number:

low: IOL / IIL = 16 mA / 1.6 mA = 10
high: IOH / IIH = 0.4 mA / 0.04 mA = 10
fan-out = the smaller = 10

CMOS inputs draw almost no current, so their fan-out is limited instead by speed: every input adds capacitance that the output must charge.

Power

A CMOS gate draws almost no current while it sits still. It uses power when it switches, charging and discharging the capacitance on its output, and that power grows with the square of the supply voltage:

C = 10 pF, f = 10 MHz, V = 5.0 V: P = 2.500 mW
C = 10 pF, f = 10 MHz, V = 3.3 V: P = 1.089 mW
C = 10 pF, f = 10 MHz, V = 1.8 V: P = 0.324 mW

That square is why supplies have fallen from 5 V to 3.3 V and below. The same circuit at 1.8 V uses about an eighth of the power it uses at 5 V.

What you learned

• A memory of 2 to the power k words of m bits has k address lines and m data lines.
• A ROM is a truth table: a decoder with OR gates. RAM can be written too; SRAM uses latches and DRAM uses capacitors that need refresh.
• Building a big memory from small chips: chips = (words ratio) x (width ratio), with a decoder choosing rows.
• A PLA programs its AND and OR arrays; a PAL only its AND array; an FPGA uses look-up tables, tiny ROMs.
• An R-2R DAC gives Vout = Vref x D / 2 to the power n; one step is Vref / 2 to the power n.
• A successive-approximation ADC finds one bit per step; a flash ADC is fastest but needs 2 to the power n, minus 1, comparators.
• Noise margins are NMH = VOH - VIH and NML = VIL - VOL. TTL fan-out is limited by current; CMOS power grows with V squared.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• ROM (read-only memory)
• RAM (random-access memory)
• Flash memory
• Volatile memory
• PLA (programmable logic array)
• PAL (programmable array logic)
• Look-up table (LUT)
• FPGA
• DAC (digital-to-analogue converter)
• Resolution
• ADC
• Quantisation error
• Flash ADC
• TTL (transistor-transistor logic)
• CMOS
• Noise margin
• Fanout

Practice

chips: (4K / 1K) x (8 / 4) = 4 x 2 = 8

10 bits, Vref 3.3 V: one step = 3.22 mV; full scale = 3.2968 V

Interview corner

Volume 10 gathers the whole course into a formula sheet and a set of GATE-style problems.