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Digital Circuits 2 marks Sequential timing Numerical answer

Maximum clock frequency from propagation, logic and setup time

BlinkNBuild practice problem · GATE standard, authored and verified in-house

In the synchronous circuit below, data launched by flip-flop FF1 propagates through a block of combinational logic and is captured by FF2 on the next rising edge of the same clock.

  • Clock-to-Q propagation delay, $t_{cq} = 2\ \text{ns}$
  • Worst-case combinational delay, $t_{logic} = 6\ \text{ns}$
  • Setup time, $t_{su} = 1\ \text{ns}$
  • Clock skew between FF1 and FF2 is zero

The maximum clock frequency, in MHz, is ________.

Two flip-flops separated by a block of combinational logic, sharing one clock, with the three delay terms labelled FF1 launch combinational t_logic = 6 ns FF2 capture t_cq = 2 ns t_su = 1 ns clk (zero skew)
Show the step-by-step derivation
Answer 111.11 MHz (accept 111 to 111.2) MHz (accept 111 to 111.2)

Step-by-step derivation

  1. Data is launched by the rising edge at $t = 0$ and must be stable at FF2's D input a setup time before the next rising edge at $t = T$. The setup constraint is therefore $$t_{cq} + t_{logic} + t_{su} \le T.$$
  2. With zero skew there is no correction term, so substituting directly: $$2 + 6 + 1 = 9\ \text{ns} \le T.$$
  3. The minimum legal period is $T_{min} = 9\ \text{ns}$, and the maximum frequency is its reciprocal: $$f_{max} = \frac{1}{T_{min}} = \frac{1}{9 \times 10^{-9}\ \text{s}}.$$
  4. Evaluating: $$f_{max} = 1.1111 \times 10^{8}\ \text{Hz} = \mathbf{111.11\ MHz}.$$
  5. Sanity check on the units: nanoseconds and megahertz are reciprocal at $1\ \text{ns} \leftrightarrow 1000\ \text{MHz}$, so $9\ \text{ns}$ must give $1000/9 = 111.1\ \text{MHz}$. ✓
The trap this question is built around Hold time never appears in the maximum-frequency equation. Hold is a constraint between the same pair of edges, so it is independent of the period - a design that fails hold fails at every frequency, including DC. Adding $t_h$ to the sum is the most common way to lose this mark.

The idea behind this question

The clock period must leave time for data to leave the launching flip-flop ($t_{cq}$), cross the logic ($t_{logic}$) and arrive a setup time early at the capturing flip-flop. That sum is the shortest legal period, and its reciprocal is the maximum frequency. Hold is a different check, between the same clock edge at both flip-flops, so it never limits frequency.

Try a variation

With $t_{cq} = 1.5$ ns, $t_{logic} = 4.5$ ns and $t_{su} = 0.5$ ns, and zero skew, what is $f_{max}$ in MHz?

Show the answer

Answer: $153.85$ MHz

$T_{min} = 1.5 + 4.5 + 0.5 = 6.5$ ns, and $1000/6.5 = 153.85$ MHz.

Other mistakes to avoid

  • Using the best-case logic delay instead of the worst case: setup must hold for the slowest path.
  • Forgetting to convert: a period in nanoseconds gives a frequency in GHz when inverted, so multiply by 1000 for MHz.

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