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Digital Circuits 1 mark CMOS logic Numerical answer

Transistor count for a static CMOS AND-OR-INVERT gate

BlinkNBuild practice problem · GATE standard, authored and verified in-house

The function $Y = \overline{(A \cdot B) + C}$ is implemented as a single complex gate in static CMOS. The total number of transistors required is ________.

Show the step-by-step derivation
Answer 6 transistors transistors

Step-by-step derivation

  1. A static CMOS gate has two networks: a pull-down network (PDN) of NMOS devices that connects the output to ground when the function is $0$, and a pull-up network (PUN) of PMOS devices that connects it to $V_{DD}$ when the function is $1$. The two are duals of each other.
  2. Pull-down network. $Y$ goes low exactly when $(A \cdot B) + C = 1$. In an NMOS network, AND becomes a series connection and OR becomes a parallel connection. So the PDN is ($A$ in series with $B$) in parallel with $C$: three NMOS transistors.
  3. Pull-up network. The PUN is the dual: series becomes parallel and parallel becomes series. So it is ($A$ in parallel with $B$) in series with $C$: three PMOS transistors.
  4. Total transistor count: $$N = N_{PDN} + N_{PUN} = 3 + 3 = \mathbf{6}.$$
  5. General rule: a static CMOS complex gate needs exactly $2n$ transistors for $n$ inputs, one NMOS and one PMOS per input. Here $n = 3$ inputs $\Rightarrow 6$ transistors - which is why AOI and OAI gates are so cheap, and why synthesis tools reach for them constantly.
The trap this question is built around Building this from discrete gates instead. An AND (6 T) plus a NOR (4 T) is 10 transistors and two gate delays. The single complex gate is 6 transistors and one gate delay, because the inversion is free - static CMOS is naturally inverting, so the bubble at the output costs nothing.

The idea behind this question

A static CMOS gate has a pull-down network of NMOS transistors and a matching pull-up network of PMOS transistors. Series connections in one network become parallel in the other. Every input drives one NMOS and one PMOS, so a single complex gate needs two transistors per input, and it naturally produces the inverted function.

Try a variation

How many transistors does the single static CMOS gate $Y = \overline{A B + C D}$ need?

Show the answer

Answer: $8$

Four inputs, and two transistors per input.

Other mistakes to avoid

  • Counting transistors for a non-inverted function, which would need an extra inverter.
  • Drawing the pull-up network in the same series-parallel arrangement as the pull-down instead of its dual.

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