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3. Static Timing Analysis from Zero
4. Volume 00

0.1 How to use this course

Static timing analysis asks one question about a chip, over and over: does the data arrive before the next clock tick? Everything else in this course is arithmetic on that question.

A chip is full of small memories called flip-flops. On every clock tick they all grab whatever is on their inputs. Between the ticks, logic works on those values and passes the results along.

If a result is late, the next flip-flop grabs the old value, or worse, a half-finished one. The chip does not warn you. It just gives wrong answers, sometimes, on some units, in some weather.

Timing analysis finds that before the chip is built. It adds up the delay on every path, compares each total with the time the clock allows, and lists anything that does not fit.

What this course does, and in what order

Take the volumes in order. Each one only uses what came before it.

How each lesson is built

1. The big idea in one sentence, so you know where the lesson is going.
2. Plain words, then an everyday picture, then the exact version.
3. Worked numbers. Every value is computed, never guessed.
4. A common mistake, because knowing the trap is half of knowing the rule.
5. A quick check at the end of each sub-module.

0.2 Clocks and flip-flops in plain words

A clock is a signal that ticks at a steady rate. A flip-flop is a one-bit memory that copies its input to its output on each tick, and holds it until the next one.

Everything in a synchronous chip moves on those ticks. Nothing happens "eventually": it happens at an edge, or it does not count.

The clock

The clock goes up and down for ever. One full up-and-down is a clock cycle, and the time it takes is the period.

The numbers above the figure count the rising edges. Timing analysis spends its whole life between two of them.

The flip-flop

A flip-flop has a data input D, a clock input, and an output Q. At each rising clock edge it looks at D and copies that value to Q. Between edges, D can do whatever it likes and Q does not care.

Read it edge by edge:

1. Edge 1. D has been 0 all cycle, so Q becomes 0.
2. Edge 2. D went high during the last cycle, so Q becomes 1.
3. Edge 4. D pulsed high and fell back before the edge, so Q becomes 0. The pulse is lost.
4. Edge 6. D rose very late in the last cycle, and Q still takes the 1.

That last one hides a question: how late is too late? The answer is the setup time, and it is the whole of Volume 04.

The three numbers every flip-flop has

Volume 02 explains where those three numbers come from. For now, just hold on to the shape of them: one describes leaving, two describe arriving.

0.3 Delay: nothing is instant

Nothing in a chip is instant. Every gate takes time, every wire takes time, and the chip's speed limit is the sum of those times along its slowest path.

A logic gate does not switch the moment its input changes. Its transistors have to charge the wire and the gates hanging off it. That takes a few tens of picoseconds.

One gate is quick. A chain of them is not.

A chain of five things

Notice the wire. It is not a gate, and it still costs 0.04 ns. On a big chip, wires often cost more than the gates they join. Volume 02 explains why.

The same delay, drawn as a path

A timing path always has the same shape: a flip-flop launches the data, some logic works on it, and another flip-flop captures it.

Add it up: 0.35 ns to leave FF1, then 0.14 + 3.42 + 0.64 = 4.20 ns of logic. The data is ready 4.55 ns after the clock edge that launched it.

Delay is not one number

The same gate is slower on a hot chip and faster on a cold one. It is slower at a low supply voltage, and slower when it drives more gates. Two chips off the same wafer differ as well.

So a delay is really a range. The chain above measures 0.41 ns typically, and this at the two ends of the range:

Both ends matter, and for different reasons. Volume 04 uses the slow numbers, Volume 05 uses the fast ones, and Volume 11 explains where the range comes from.

0.4 Reading a timing diagram

A timing diagram is a picture of signals against time. Time runs left to right, each signal has its own row, and everything interesting happens at an edge.

You have already read two of them. This sub-module makes the habit explicit, because every later volume shows its argument as a waveform.

How to read one, every time

1. Find the clock row first. It sets the beat for everything below it.
2. Number the rising edges. The lessons print those numbers above the figure.
3. Pick the edge that launches your data. Everything is measured from there.
4. Follow the row below it. A signal that changes does so just after an edge, not on it.
5. Find the edge that captures it. The gap between the two edges is the time you have.

Reading it in order: at edge 1, FF1 copies its input and its output q1 rises. That new value travels through the logic, and appears at FF2's input d2 partway through the cycle. At edge 2, FF2 copies it, so q2 rises one cycle later.

What the diagram cannot show

A waveform is not to scale. A 0.35 ns clock-to-Q delay and a 4.20 ns adder would be invisible next to a 10 ns cycle, so figures exaggerate them. When a number matters, this course writes it down as well as drawing it.

0.5 Units: ns, ps, MHz and GHz

Frequency and period are the same fact said two ways. Divide 1000 by a frequency in MHz and you get the period in nanoseconds.

Timing is measured in small units, and mixing them up is the easiest way to get a wrong answer. Here they are, once, clearly.

So 1 ns = 1000 ps, and 0.25 ns = 250 ps. This course writes path delays in ns and small numbers in either, because engineers do: "the adder is 3.42 ns" and "setup is 150 ps" are both normal.

Frequency to period

A GHz is a thousand MHz, so 2.5 GHz is 2500 MHz and 1000 / 2500 = 0.4 ns. The same sum works backwards: a 4 ns period is 1000 / 4 = 250 MHz.

Getting a feel for it

1. 500 ps + 1.2 ns = 1.7 ns. Convert first, then add.
2. Six gates of 80 ps each = 0.48 ns.
3. One 100 MHz cycle is 10 ns, so about 125 of those gates fit end to end in it.
4. Light travels about 30 cm in one nanosecond, and about 0.30 mm in one picosecond.

That last line is worth keeping. When a lesson says a wire costs 40 ps, it is talking about a distance a beam of light would cross in about a centimetre. Electricity in a chip wire is slower still.

What you learned

• Static timing analysis adds up delays on every path and checks each one against the clock.
• A clock ticks steadily; a flip-flop copies D to Q at each rising edge and holds it.
• Every flip-flop has three numbers: clock-to-Q, setup time and hold time.
• Nothing is instant: gates and wires both take time, and the slowest path sets the speed limit.
• Delay is a range, not a number. It changes with temperature, voltage, load and manufacturing.
• In a timing diagram, time runs left to right and signals change just after an edge.
• Period in ns = 1000 / frequency in MHz, and 1 ns = 1000 ps.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Static timing analysis (STA)
• Clock
• Flip-flop
• Clock cycle
• Rising edge
• Clock edge
• Setup time
• Clock-to-Q delay
• Hold time
• Logic gate
• Picosecond (ps)
• Timing diagram
• Nanosecond (ns)

Practice

Interview corner

Volume 01 turns this into a race: the data running down the path against the clock running down its own, with two ways to lose.