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3. Static Timing Analysis from Zero
4. Volume 03

3.1 Start points and end points

Every timing path begins where data is launched and ends where data is captured. There are only two kinds of beginning and two kinds of end, and that is what lets a tool find every path in a chip.

A timing tool does not try to understand your design. It breaks it into pieces it can time one at a time: paths. Each path has exactly one start point and one endpoint.

Why the clock pin and not the Q output? Because the data does not leave the flip-flop until the clock edge arrives there. The path really begins with the clock edge, and the clock-to-Q delay is its first step.

Every path in a small design

Here is a design small enough to list completely: two inputs, three flip-flops and one output. U1 is an AND gate, U2 an XOR gate, U3 an OR gate, and FF3's output also feeds FF1 directly, with no logic at all.

Seven paths, from five start points (FF1/CK, FF2/CK, FF3/CK, in_a, in_b) to four endpoints (FF1/D, FF2/D, FF3/D, out_y). The tool times each one separately, and each gets its own slack.

Notice path 7. It has no logic at all, just a wire. It still counts, and it is exactly the kind of path that fails hold, because nothing slows it down.

3.2 The four path types

Two kinds of start and two kinds of end make four kinds of path. Every report sorts its paths into these four, and each is timed with the same arithmetic.

All four use the same sum as Volume 01: the data arrives at some time, it is needed by some time, and the difference is the slack. What changes is where the two times come from.

An input delay says: the outside world launched this data on the same clock, and it has already spent this long getting here. An output delay says: the outside world needs this much time after our output to reach its own flip-flop. Volume 10 covers both properly.

All four, timed at 100 MHz

1. Input to register. Input delay 3.00 + AND2 0.14 + wire 0.30 = 3.44 ns. Needed by 10 - 0.15 = 9.85 ns.
2. Register to output. Clock-to-Q 0.35 + OR2 0.16 + output pad 0.90 = 1.41 ns. Needed by 10 - 4.00 = 6.00 ns.
3. Input to output. Input delay 2.00 + OR2 0.16 + output pad 0.90 = 3.06 ns. Needed by 6.00 ns.

3.3 Launch edge and capture edge

Every check compares two clock edges: the one that launched the data and the one that captures it. For an ordinary path they are one period apart for setup, and the very same edge for hold.

The launch edge sends the data. The capture edge is the one the setup check races against. Choosing the right pair of edges is the first thing a tool does for every path.

Three ways to pair the edges on one clock

A flip-flop can act on the rising edge, or on the falling one. That gives different pairs:

Clock of 10 ns with a 50% duty cycle. A path from a rising-edge flop to a falling-edge flop gets only half a period for setup. But its hold check becomes easy, because the capture edge it is checked against came half a period before the launch.

3.4 Timing arcs and unateness

A timing arc says which input change causes which output change, and how long it takes. Rising and falling edges have different delays, so a tool follows both, all the way along the path.

Inside a gate, pulling the output up and pulling it down are done by different transistors. They are not equally strong, so a gate's rising delay and falling delay differ. The library stores both.

And not every input edge causes the same output edge. That relationship has a name, unateness.

Following rise and fall down a chain

Take a path through four gates, starting from a flip-flop whose Q rises at 0.36 ns or falls at 0.33 ns after the clock edge. Each gate has its own rise and fall delay.

The latest arrival at the end is 0.66 ns. For hold, the tool runs the same walk taking the earlier edge at the XOR, and gets 0.63 ns.

Why not just add the worst delay of each gate?

Adding each gate's slower delay, ignoring which edge is which, gives 0.36 + 0.05 + 0.08 + 0.12 + 0.08 = 0.69 ns. That is 0.03 ns worse than any real edge can be. An edge cannot be a rise and a fall at the same time, and following the arcs knows that.

3.5 Clock paths versus data paths

The clock has a path too: from its source, through the clock tree, to every flip-flop. A tool times it separately, and only the difference between the launch and capture clock arrivals changes the slack.

So far the clock edge has reached both flip-flops at the same instant. It never does. The clock starts at one place and is carried to every flip-flop by a tree of buffers and wires. That takes time: the clock latency.

The arithmetic, with the clock paths in

1. Arrival. Launch edge at 0, plus 0.85 to reach FF1, plus clock-to-Q 0.35, plus logic 4.20 = 5.40 ns.
2. Required. Capture edge at 10, plus 0.90 to reach FF2, less setup 0.15 = 10.75 ns.
3. Slack. 10.75 - 5.40 = 5.35 ns.

Without the clock tree the slack was 5.30 ns. With it, it is 5.35 ns: 0.05 ns better. That 0.05 ns is exactly how much later the clock reaches FF2 than FF1.

Only the difference matters

Add two whole nanoseconds to both clock paths and nothing changes. Swap them, and setup gets worse while hold gets better. That difference is clock skew, and Volume 06 treats it in full.

What you learned

• A path starts at a flip-flop's clock pin or an input port, and ends at a data pin or an output port.
• That gives four path types, all timed with the same arrival-against-required sum.
• Input and output paths depend on the delays you declare for the world outside the design.
• Setup compares the launch edge with the next capture edge; hold compares it with one edge earlier.
• A timing arc links an input edge to an output edge; unateness says which edge causes which.
• Tools follow rise and fall separately, which is less pessimistic than adding worst delays.
• The clock has its own path; only the difference in arrival between the two flip-flops moves slack.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Start point
• Endpoint
• Input port
• Output port
• Input delay
• Output delay
• Launch edge
• Capture edge
• Timing arc
• Unateness
• Clock tree
• Clock latency
• Clock skew

Practice

Interview corner

Volume 04 takes the register-to-register path and does setup analysis properly. Arrival time, required time and slack are built one term at a time, with ten worked problems and a real report read line by line.