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3. Static Timing Analysis from Zero
4. Volume 04

4.1 Arrival time

The arrival time is when the data really reaches the capture flip-flop. It is built by starting at the launch edge and adding every delay the data meets, in the order it meets them.

Volume 01 did this with three numbers. A real path has more, and each one is there for a reason. This volume uses one path throughout, on a 200 MHz clock (5.00 ns).

Build it, term by term

The first three steps are the clock. The data cannot leave u_ff1 until the clock edge has got there, so 1.06 ns passes before the data even starts moving. The logic itself is 2.89 ns.

4.2 Required time

The required time is the deadline. It starts at the capture edge, adds the time the clock takes to reach the capture flip-flop, and then takes off two margins: the clock uncertainty and the setup time.

Why is the clock latency added? Because the capture edge also has to travel. It reaches u_ff2 0.88 ns after it leaves the source, so the flip-flop actually captures at 5.88 ns, not at 5.00 ns.

Clock uncertainty

A clock is never perfect. Its edges wobble a little from cycle to cycle, and early in a project the clock tree does not exist yet. So a margin is taken off every setup check: the clock uncertainty. Here it is 0.08 ns.

4.3 Setup slack

Setup slack is the required time minus the arrival time. Everything in this sub-module is that one subtraction, looked at from different sides.

For the Volume 04 path:

The path has 1.76 ns to spare.

The same sum on one line

Put both sides together, and let the source latency cancel. What is left is worth memorising:

Here, skew is the capture clock arrival minus the launch clock arrival: 0.88 - 0.85 = +0.03 ns.

5.00 + 0.03 - 0.21 - 2.89 - 0.09 - 0.08 = 1.76 ns, the same answer.

What the sign tells you

4.4 Ten worked setup problems

Setup analysis is learned by doing it. Ten problems follow, each adding one idea. Try each one before opening its answer.

Use the one-line formula: slack = T + skew - clock-to-Q - logic - setup - uncertainty, where skew is the capture clock arrival minus the launch clock arrival.

4.5 Maximum frequency

A path's shortest possible period is its current period minus its slack. The maximum frequency of the whole design is set by the path whose shortest period is the longest.

Slack moves one-for-one with the period: take 1 ns off the period and the slack drops by exactly 1 ns. So the period at which the slack would be zero is easy to find.

For the Volume 04 path: 5.00 - 1.76 = 3.24 ns, and 1000 / 3.24 = 308.6 MHz.

The whole design runs at its worst path's speed

A design has many paths. Each one has its own shortest period, and the chip can go no faster than the longest of them.

This design runs at 264.6 MHz. The other two paths could go faster, but that does not help: the longer path is the critical path.

4.6 Reading a setup report line by line

A timing report is this volume's arithmetic, printed by the tool. Read it as two columns of stopwatch times, one for the data and one for the deadline, and it holds no surprises.

Here is the setup report for the Volume 04 path, in the layout sign-off tools use.

Startpoint: u_ff1
Endpoint:   u_ff2
Path Group: clk
Path Type:  max

  Point                                              Incr     Path
  ----------------------------------------------------------------
  clock clk (rise edge)                              0.00     0.00
  clock source latency                               0.50     0.50
  clock network delay (propagated)                   0.35     0.85
  u_ff1/CK                                           0.00     0.85
  u_ff1/Q (clock-to-Q)                               0.21     1.06
  u1/Y (NAND2_X1)                                    0.12     1.18
  u2/Y (XOR2_X1)                                     0.23     1.41
  u_add/S (ADD16_X1)                                 2.10     3.51
  u3/Y (AOI21_X1)                                    0.18     3.69
  u4/Y (MUX2_X2)                                     0.26     3.95
  u_ff2/D                                            0.00     3.95
  data arrival time                                           3.95

  clock clk (rise edge)                              5.00     5.00
  clock source latency                               0.50     5.50
  clock network delay (propagated)                   0.38     5.88
  u_ff2/CK                                           0.00     5.88
  clock uncertainty                                 -0.08     5.80
  library setup time                                -0.09     5.71
  data required time                                          5.71
  ----------------------------------------------------------------
  data required time                                          5.71
  data arrival time                                          -3.95
  ----------------------------------------------------------------
  slack (MET)                                                 1.76

Line by line

1. The header. Startpoint and Endpoint name the two flip-flops. "Path Type: max" means the slow delays were used: this is a setup check.
2. Incr and Path. Incr is what each line adds. Path is the running total - the stopwatch.
3. The top half is the arrival. Launch edge at 0, the clock reaching u_ff1 at 0.85, then clock-to-Q and each cell. Each cell line is named by its output pin and its cell type.
4. "data arrival time" is 3.95, the same number sub-module 4.1 built.
5. The bottom half is the deadline. The capture edge at 5.00, the clock reaching u_ff2 at 5.88, then the uncertainty and setup taken off. The deadline is 5.71.
6. The last three lines subtract the two, and give the slack with its verdict: MET.

What to look at first

When a path fails, read the Incr column, not the Path column. Here the adder alone is 2.10 of the 2.89 ns of logic: 73%. That one line is where any fix would start.

What you learned

• Arrival time adds the launch clock latency, clock-to-Q and every delay after the launch edge.
• Required time adds the capture clock latency to the capture edge, then subtracts uncertainty and setup.
• Setup slack is required minus arrival: T + skew - clock-to-Q - logic - setup - uncertainty.
• The logic budget is what is left of the period after everything that is not logic.
• A path's shortest period is T minus its slack; the design's f_max is set by its worst path.
• A timing report is the same sum: the arrival on top, the deadline below, the slack at the end.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Arrival time
• Required time
• Clock uncertainty
• Maximum clock frequency (fmax)
• Critical path
• Timing report
• Pipelining

Practice

Interview corner

Volume 05 does the same for hold: the same stopwatch, but with the fastest delays, the same clock edge at both ends - and no clock period anywhere in the sum.