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3. Static Timing Analysis from Zero
4. Volume 11

11.1 PVT corners

A PVT corner is one set of conditions - process, voltage, temperature - at which every delay on the chip is worked out. Setup is signed off at the slowest corner, hold at the fastest, because that is where each one fails.

Volume 02 showed a gate slowing down when the chip is hot, the supply is low, or the manufacturing came out slow. Those three move together across the whole chip, so a timing tool runs the whole analysis again at each extreme.

The same two paths at three corners

Take the adder path from Volume 04 and a short one-buffer path, on the 5 ns clock. Scale every delay by the corner's factor, and check both:

The library setup and hold times are kept fixed here to keep the sums clear; real libraries give them per corner too.

The long path's setup is worst at the slow corner, where its delay has grown most. The short path's hold is worst at the fast corner, where its data rushes through. Each check has its own worst corner.

11.2 RC corners

Wires vary too, and their resistance and capacitance do not always move together. The slowest RC corner for a short wire is not the slowest one for a long wire.

A metal line can come out a little thicker or thinner, wider or narrower, than drawn. A wider wire has less resistance but more capacitance to its neighbours. So RC corners come in pairs of opposites:

The wires are driven through 1 kOhm into 5 fF, as in Volume 02. On the short wire, the driver's charging of the wire's capacitance dominates, so the corner with the most capacitance is slowest: Cworst. On the long wire, the wire's own resistance matters most, so RCworst is slowest.

11.3 On-chip variation and derating

Corners treat the whole chip as uniformly slow or fast. But gates on one chip also differ from each other. On-chip variation is covered by derating: pushing some delays slower and others faster, to assume the worst mix.

Even at the slow corner, the gates on one chip are not all equally slow. One corner of the die may be a little hotter; one cell may have come out a little different. Timing has to assume the unlucky mix.

For setup, the unlucky mix is: the launch clock and the data path slow, the capture clock fast. For hold it is the reverse. A derate of 5% means multiplying the "slow" side by 1.05 and the "fast" side by 0.95.

The adder path at the slow corner, derated

The path that passed at the slow corner fails once on-chip variation is added. That is the whole point: the corner covers the chip being slow, the derate covers it being unevenly slow.

set_timing_derate -late  1.05
set_timing_derate -early 0.95

11.4 AOCV and POCV, simply

A flat derate assumes every gate on a path is unlucky at once. Real variation is partly random, and random differences tend to cancel over many gates. AOCV and POCV use that to remove pessimism.

AOCV: deeper paths get a smaller derate

If each gate's variation is random, a path of many gates averages it out. So AOCV looks up the derate from a table by the path's logic depth. A typical shape shrinks with the square root of the depth:

POCV: add the spreads, not the worst cases

POCV goes one step further. Each cell has an average delay and a spread, its sigma. The tool adds the averages, and combines the spreads statistically - as the square root of the sum of their squares.

Take the adder path's five cells, each with a sigma of 5% of its delay:

POCV removes 0.113 ns of pessimism on this one path. It removes more on paths with many similar cells: eight cells of 0.30 ns come out at 2.760 ns flat, but 2.527 ns with POCV.

11.5 Clock reconvergence pessimism (CRPR)

Suppose the launch and capture clocks share part of the clock tree. Derating then treats that shared part as slow on one side and fast on the other, at the same moment. That is impossible, and CRPR gives the difference back.

Where the pessimism comes from

Derate the clock tree by 5% each way, for a setup check:

1. Launch clock, made late: (0.60 + 0.25) x 1.05 = 0.8925 ns.
2. Capture clock, made early: (0.60 + 0.28) x 0.95 = 0.8360 ns.
3. The shared 0.60 ns was counted as 0.630 ns on one side and 0.570 ns on the other. One piece of wire cannot be both at once.
4. CRPR credit: 0.630 - 0.570 = 0.060 ns, given back to the check.

In the report

Startpoint: u_launch
Endpoint:   u_capture
Path Group: clk
Path Type:  max

  Point                                              Incr     Path
  ----------------------------------------------------------------
  clock clk (rise edge)                              0.00     0.00
  clock network delay (propagated)                   0.89     0.89
  u_launch/CK                                        0.00     0.89
  u_launch/Q (clock-to-Q)                            0.22     1.11
  logic                                              3.03     4.15
  u_capture/D                                        0.00     4.15
  data arrival time                                           4.15

  clock clk (rise edge)                              5.00     5.00
  clock network delay (propagated)                   0.84     5.84
  u_capture/CK                                       0.00     5.84
  clock reconvergence pessimism                      0.06     5.90
  clock uncertainty                                 -0.08     5.82
  library setup time                                -0.09     5.73
  data required time                                          5.73
  ----------------------------------------------------------------
  data required time                                          5.73
  data arrival time                                          -4.15
  ----------------------------------------------------------------
  slack (MET)                                                 1.58

The clock reconvergence pessimism line sits on the required side, and adds the 0.06 ns back. The clock and logic lines above it are already derated: 3.03 ns of logic is 2.89 ns x 1.05.

What you learned

• PVT corners scale every delay together; setup is signed off slow, hold fast.
• RC corners vary wire resistance and capacitance; the worst one depends on the wire's length.
• On-chip variation is covered by derating: one side slower, the other faster.
• AOCV shrinks the derate for deeper paths; POCV adds cell spreads statistically.
• A shared clock trunk derated both ways is impossible pessimism, and CRPR gives it back.
• Sign-off checks every combination of PVT corner, RC corner and mode.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• PVT corner
• RC corner
• On-chip variation (OCV)
• Derating
• AOCV
• POCV
• Sigma
• CRPR

Practice

Interview corner

Volume 12 turns to a different kind of variation: a delay that changes because a neighbouring wire switches at the same moment.