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3. Static Timing Analysis from Zero
4. Volume 13

13.1 Defining clocks

Every timing check starts from a clock, and a tool only knows the clocks you declare. Primary clocks are created on the pins where they enter; every clock made inside the design is declared as generated from one of them.

SDC is the constraint language nearly every timing tool reads. It is Tcl: one command per line, read from top to bottom. This volume collects every command the course has used, in the order a constraint file usually follows.

Primary clocks

# a 100 MHz clock arriving on port clk, rising at 0 and falling at 5
create_clock -name clk -period 10 -waveform {0 5} [get_ports clk]

# a clock for another chip, with no pin in this design (Volume 10)
create_clock -name vclk -period 10 -waveform {2 7}

Generated clocks

A generated clock names a master and says how its edges come from the master's. The -edges option numbers the master's edges from the first rising one: 1 rises, 2 falls, 3 rises, and so on. It gives three numbers - the new clock's rise, fall and next rise.

create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins u_div2/Q]
create_generated_clock -name clk_div3 -source [get_ports clk] -edges {1 4 7} [get_pins u_div3/Q]

13.2 Clock properties

A clock also carries properties: how long it takes to arrive, how much it wobbles, and how sharp its edges are. Most of them change once the clock tree is built.

# where the clock comes from (Volume 06): off-chip PLL to our clock pin
set_clock_latency -source 0.50 [get_clocks clk]

# before the clock tree exists: an estimate of its delay
set_clock_latency 0.40 [get_clocks clk]

# jitter plus margin (setup), margin only (hold) - Volumes 04 and 06
set_clock_uncertainty -setup 0.08 [get_clocks clk]
set_clock_uncertainty -hold  0.03 [get_clocks clk]

# the edge speed at the flip-flops, before the tree is built
set_clock_transition 0.10 [get_clocks clk]

# after clock tree synthesis: measure the real tree instead
set_propagated_clock [all_clocks]

13.3 I/O constraints

An input needs more than an input delay: the tool also wants to know how sharp its edge is. An output needs more than an output delay: the tool wants to know how much it drives. Leave either out and the first and last gates of the path are timed with made-up numbers.

# Volume 10: from the other chip's datasheet
set_input_delay  -clock clk -max 4.80 [get_ports in_data]
set_input_delay  -clock clk -min 1.50 [get_ports in_data]
set_output_delay -clock clk -max 2.70 [get_ports out_data]
set_output_delay -clock clk -min -0.10 [get_ports out_data]

# how the input is driven, and what the output drives
set_input_transition 0.40 [get_ports in_data]
set_load 0.020 [get_ports out_data]

Why they matter, using the NAND2_X1 from Volume 02:

set_load takes the load in the library's capacitance unit, often picofarads - so 0.020 is 20 fF. A real design would often use set_driving_cell instead of set_input_transition, naming a library cell whose strength matches the outside driver.

13.4 Exceptions

Exceptions change how particular paths are timed. When two could apply to the same path, a fixed order decides: a false path beats a max or min delay, which beats a multicycle path.

# unrelated clocks: time nothing between them
set_clock_groups -asynchronous -group [get_clocks clk_a] -group [get_clocks clk_b]

# a path that can never happen
set_false_path -through [get_pins u_mux1/I0] -through [get_pins u_mux2/I1]

# three cycles for setup, and the hold check put back
set_multicycle_path 3 -setup -from [get_cells u_src] -to [get_cells u_dst]
set_multicycle_path 2 -hold  -from [get_cells u_src] -to [get_cells u_dst]

# a bound on a crossing between unrelated clocks
set_max_delay -datapath_only 3.0 -from [get_cells wptr_gray_reg*] -to [get_cells wptr_sync1_reg*]

# one mode at a time
set_case_analysis 0 [get_ports test_mode]

Which exception wins

When two exceptions of the same kind cover a path, the more specific one wins. A -from naming a pin beats one naming a cell, and a cell beats a whole clock.

13.5 Design rules: transition, capacitance, fanout

Design rules are limits on every net, not on paths: how slow an edge may be, how much load a gate may drive, and how many inputs it may feed. They keep gates inside the part of their tables that the library measured.

set_max_transition  0.150 [current_design]
set_max_capacitance 0.025 [current_design]
set_max_fanout      12    [current_design]

Here is the NAND2_X1 from Volume 02, driving a fanout of 16 (29 fF), against those limits:

There are two fixes, both from Volume 02. Drive the net with a NAND2_X4, whose edge is 47.8 ps. Or split it into two nets of 8 loads, 14.5 fF apiece, whose edges are 95.6 ps each. Either one meets every rule.

13.6 Checking your constraints

A timing report only shows problems with paths it could time. A path with a missing constraint is not failing - it is unconstrained, and it is silent. Checking the constraints is its own step.

Go back to the small design of Volume 03, with its seven paths. Suppose the constraint file forgot the input delay on in_b. Two paths now start from a port the tool knows nothing about:

Here is the trap. FF3/D and out_y still receive other, timed paths - from FF2 and FF3. So neither endpoint looks unconstrained. The report shows no violation, and nothing seems wrong, but two paths in seven are simply not checked.

What to run, and read

1. A constraint check (check_timing in many tools): lists unclocked registers, inputs and outputs with no delay, generated clocks with no master, and combinational loops.
2. A list of the clocks the tool created, with their periods, waveforms and sources. Compare it with what you meant.
3. A list of the exceptions the tool applied, and to how many paths each. An exception that matched nothing is a typo; one that matched thousands of paths deserves a second look.
4. A count of unconstrained endpoints and paths. On a finished design it should be zero, or every one explained.

What you learned

• Primary clocks are created on pins; clocks made inside the design are generated from a master.
• -edges counts master edges from the first rise: odd numbers rise, even numbers fall.
• Clock latency, uncertainty and transition are set by hand before the clock tree, and mostly measured after.
• Inputs need a delay and an edge speed; outputs need a delay and a load.
• A false path beats a max or min delay, which beats a multicycle path; the more specific exception wins.
• Design rules limit every net's transition, capacitance and fanout.
• A missing constraint does not fail - it goes silent, so constraints must be checked on their own.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• SDC (Synopsys Design Constraints)
• Design rules
• Unconstrained path

Practice

Interview corner

Volume 14 puts everything to work. What do you do when the slack is negative, for setup and for hold, on an FPGA and on an ASIC? It ends with one design closed from its first report to its last.