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Guide 6 paths

Learning Paths: Where to Start and What to Take Next

Each path is an order to take the courses in, chosen for one goal. Pick the job you want, follow the steps from the top, and skip anything you already know.

Choose your path

  1. Digital design (RTL)You want to design the logic inside chips - processors, accelerators and controllers. This path leads to an RTL design role.7 live steps
  2. FPGA engineerYou want to build working hardware on a board - prototypes, video pipelines, motor control or custom accelerators.7 live steps
  3. Verification engineerYou want to prove that designs work before they become silicon - with testbenches, coverage, assertions and UVM.4 live steps
  4. Physical design (ASIC)You want to turn RTL into a real chip layout - synthesis, floorplanning, placement, routing and sign-off.5 live steps
  5. Embedded systemsYou want to write the software that runs on microcontrollers and talks directly to hardware.5 live steps
  6. GATE ECE preparationYou are preparing for GATE Electronics and Communication, and want the digital circuits questions to be easy marks.6 live steps
Not sure where to start?

Start with State Machines from Zero. It assumes nothing: its first volume teaches the few ideas you need, in under an hour. Most paths below use it, so no time is wasted whichever way you go next.

Digital design (RTL)

You want to design the logic inside chips - processors, accelerators and controllers. This path leads to an RTL design role.

  1. 01Digital Logic from ZeroThe whole course, 11 volumes - Start here if you are completely new: bits, gates, Boolean algebra and flip-flops, from zero.Course
  2. 02Electronics from ZeroVolumes 05-06 - How a logic gate is really built from transistors, and where a chip's power goes.Course
  3. 03State Machines from ZeroThe whole course, 15 volumes - Then circuits that remember and decide: state machines, built up from the first flip-flop.Course
  4. 04Verilog & SystemVerilogVolumes 01-07 - The language of chip design, from combinational logic to clock crossings and timing.Course
  5. 05FSM StudioDesign a machine, read the Verilog it writes, and test it.Tool
  6. 06Verilog & SystemVerilogVolumes 08 and 10-11 - SystemVerilog for design, then the revision and interview vaults.Course
  7. 07Static Timing Analysis from ZeroVolumes 01, 03-08 and 13-14 - Every timing check an RTL designer meets: setup, hold, clocks, exceptions, SDC and closure.Course
  8. 08Clock Domain Crossing, CompleteSynchronisers, handshakes and asynchronous FIFOs in full.Planned course
  9. 09Build a RISC-V CPUPut it all together in a processor of your own.Planned course

FPGA engineer

You want to build working hardware on a board - prototypes, video pipelines, motor control or custom accelerators.

  1. 01State Machines from ZeroVolumes 00-08 - The foundations, up to real controllers such as a UART and an SPI master.Course
  2. 02Verilog & SystemVerilogVolumes 01-06 - Write the RTL, including clock-domain crossings, memories and FIFOs.Course
  3. 03FPGA MasteryThe whole course, 7 volumes - From FPGA architecture and the Vivado flow to AXI, Zynq and bring-up on a real board.Course
  4. 04Verilog & SystemVerilogVolume 07 - Static timing analysis, for the day a design will not meet its clock.Course
  5. 05Static Timing Analysis from ZeroVolumes 04-05, 07-08 and 10 - Setup, hold, several clocks, exceptions and I/O timing: the checks behind every XDC file.Course
  6. 06Embedded C from ZeroVolumes 09-11 and 13 - The software half of a Zynq design: the memory map, registers, interrupts and drivers for the buses you just built.Course
  7. 07Electronics from ZeroVolumes 07-08 - Power supplies, decoupling, datasheets and bench tools: what you need when a board will not start.Course
  8. 08Protocols from ZeroUART, SPI, I2C, CAN and the on-chip buses, from both sides.Planned course

Verification engineer

You want to prove that designs work before they become silicon - with testbenches, coverage, assertions and UVM.

  1. 01State Machines from ZeroVolumes 00-06 - Learn how the designs you will test are built.Course
  2. 02State Machines from ZeroVolume 12 - Coverage, assertions and formal checks, explained in plain words.Course
  3. 03FSM StudioGenerate a self-checking testbench and watch transition coverage fill up.Tool
  4. 04Verilog & SystemVerilogVolumes 08-09 - SystemVerilog for design and verification: classes, randomisation, coverage and assertions.Course
  5. 05UVM from ZeroThe industry-standard verification method, one idea at a time.Planned course
  6. 06Formal VerificationProving that a property holds for every possible input.Planned course

Physical design (ASIC)

You want to turn RTL into a real chip layout - synthesis, floorplanning, placement, routing and sign-off.

  1. 01Verilog & SystemVerilogVolumes 01-03 - Enough RTL to understand what the tools are building.Course
  2. 02State Machines from ZeroVolume 13 - Why the structure of a design sets its clock speed - a gentle start on timing.Course
  3. 03Verilog & SystemVerilogVolume 07 - Static timing analysis: the language of every physical design review.Course
  4. 04ASIC & Physical DesignThe whole course, 6 volumes - The whole open-source flow on Sky130, from the PDK to a finished layout.Course
  5. 05Static Timing Analysis from ZeroThe whole course, 16 volumes - Timing in full depth: every check, every corner and mode, and how to close it.Course
  6. 06Low-Power DesignClock gating, power domains and the other ways to save energy.Planned course

Embedded systems

You want to write the software that runs on microcontrollers and talks directly to hardware.

  1. 01Electronics from ZeroThe whole course, 9 volumes - Start here if you have never built a circuit: voltage, current, LEDs, transistor switches, pull-ups and power supplies, from zero.Course
  2. 02State Machines from ZeroVolumes 00-02 and 07-08 - State machines run most firmware too: button handlers, protocol drivers and menus.Course
  3. 03Embedded C from ZeroThe whole course, 19 volumes - C from the first line to interrupts, drivers and debugging, with every example compiled and run before it was published.Course
  4. 04FPGA MasteryVolume 06 - Zynq: where software on an Arm core meets hardware you designed yourself.Course
  5. 05Embedded C++The whole course, 11 volumes - C++ for small devices: classes, RAII and templates without the cost, a driver layer, and tests on your PC, with every cost measured.Course
  6. 06Microcontrollers and RTOSTimers, DMA, low-power modes and real-time operating systems.Planned course

GATE ECE preparation

You are preparing for GATE Electronics and Communication, and want the digital circuits questions to be easy marks.

  1. 01GATE ECE portalSolved questions in all eight subjects, with every step shown.Practice
  2. 02Digital Logic from ZeroThe whole course, 11 volumes - Number systems, Boolean algebra, K-maps, adders, flip-flops and counters, from zero - with GATE-style practice problems in the last volume.Course
  3. 03State Machines from ZeroVolumes 01-03, 06-07 and 10 - Sequential circuits, counters, sequence detectors and state minimisation, from the ground up.Course
  4. 04GATE digital circuits questionsTest yourself on exam-style digital questions.Practice
  5. 05Electronics from ZeroVolumes 02-06 - A gentle start on networks and devices: Kirchhoff's laws, RC circuits, diodes, transistors and CMOS gates.Course
  6. 06State Machines from ZeroVolume 14 - Thirty more solved design problems, and a one-page revision sheet.Course

Steps marked Planned course are on the Academy's roadmap. Until they arrive, the live steps around them already make a complete path.