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4. Volume 14

14.1 Fixing setup violations

A setup violation is fixed in one of two ways: make the path faster, or give it more time. The fixes differ hugely in how much they buy and what they cost, so the first step is always to read where the time goes.

Timing closure is the work of changing a design until every path passes. This volume uses the adder path again, now at 250 MHz (4 ns), with slow-corner delays, since that is where setup is signed off.

Read the Incr column first. The adder is 2.60 of the 3.77 ns of logic. The multiplexer, 0.42 ns, is slow for such a small cell - a sign it is too weak for its load.

Every fix, measured

1. Upsizing is cheap and local, but buys little: a stronger gate only helps where the load was the problem.
2. Low-Vt cells are faster versions of the same cells. They leak more power while idle, so they go only where needed.
3. A different architecture buys the most, but it is a design change, made early or not at all.
4. Useful skew moves time from the next stage, as in Volume 06; that stage must have it to spare.
5. Pipelining splits the path, at the cost of a cycle of latency the design must be able to accept.

14.2 Fixing hold violations

Hold violations are fixed by adding delay to the short path, usually with delay cells. Every cell added for hold also slows the path for setup, so each fix must be checked at the slow corner too.

A delay cell adds delay at the fast corner, where hold is checked. It also adds more delay at the slow corner, where setup is checked. Take delay cells of 0.04 ns at the fast corner and 0.06 ns at the slow one:

The cells needed are the hold violation divided by 0.04 ns, rounded up. Three fixes are clean. P3 is the trap: its hold is fixed, but its setup now fails.

When a hold fix breaks setup

P3 has a short path and a long path meeting at the same capture flip-flop - one sets its hold, the other its setup. A delay cell at the flip-flop's input slows both. The answer is to put the delay only on the short branch, before the paths join, or to fix the skew instead of the data path.

14.3 Engineering change orders (ECOs)

An ECO is a small, targeted change to a nearly finished design - resizing a few cells, adding a few delay cells - made without running the whole flow again. The later it comes, the smaller and more careful it must be.

Near the end of a project, running synthesis and place-and-route again would change thousands of cells, and every timing result with them. So the last fixes are made as ECOs: a list of exact changes, applied in place, with the rest of the design left untouched.

Metal-only ECOs

After the masks for the transistors are made, a change can still be made by altering only the metal wiring layers, which is far cheaper. It works because designers scatter spare cells - unused gates - across the chip in advance. A metal-only ECO connects them in.

14.4 Closure on FPGA versus ASIC

The arithmetic of closure is the same on an FPGA and an ASIC, but the levers are not. An FPGA's cells are fixed and its wires are slow, so closure there is mostly about placement, routing and pipelining.

On an ASIC you choose every cell's size and threshold voltage. On an FPGA the logic cells are fixed, and most of a path's delay is routing between them. Take a path at 300 MHz (3.333 ns), with five look-up tables of 0.12 ns and five routes of 0.60 ns:

The FPGA tools that do this work are covered hands-on in FPGA Mastery Volume 02. For the ASIC side, see the clock tree and useful skew in ASIC Volume 04, and the sign-off loop in ASIC Volume 06.

14.5 A full closure walkthrough

Real closure is a loop: time the design, fix the worst problems, and time it again - first for setup, then, once the clock tree exists, for hold. WNS and TNS track the progress.

A small design of five paths at 250 MHz. Setup is checked at the slow corner and hold at the fast one. WNS is the worst slack; TNS adds up every failing slack.

Step 1 - after placement, with an ideal clock

Setup WNS -0.25 ns, TNS -0.39 ns, two paths failing. The uncertainty is still the early estimate: 0.18 ns for setup and 0.13 ns for hold. Hold looks clean - for now.

Step 2 - setup fixes

Path A gets its multiplexer upsized and its adder in low-Vt cells. Path B's multiplier is restructured, from 3.66 to 3.40 ns.

Setup WNS +0.12 ns. Every setup check passes. Notice that B's hold slack dropped from 1.18 to 1.08 ns: the restructured logic is faster at both corners.

Step 3 - after clock tree synthesis

The clock is now propagated through a real tree, and the uncertainty drops to 0.08 ns and 0.03 ns.

Setup improved, because the pessimistic early uncertainty is gone. But hold now fails on D and E. The real tree reaches their capture flip-flops 0.19 and 0.17 ns late - skew no estimate predicted. Hold WNS -0.05 ns, TNS -0.06 ns.

Step 4 - hold fixes

D gets two delay cells, E gets one.

Every check passes: setup WNS +0.16 ns, hold WNS +0.03 ns. D and E had setup slack to burn, so their delay cells cost nothing that mattered.

What you learned

• Read where the delay goes before choosing a fix; use the biggest lever on the biggest delay.
• Setup is fixed by faster cells, better structure, useful skew or pipelining.
• Hold is fixed with delay cells, and every one must be re-checked for setup at the slow corner.
• ECOs make small, exact changes late in a project; spare cells allow metal-only fixes.
• FPGA closure relies on placement and pipelining, because its cells are fixed.
• Closure runs in order: setup with an ideal clock, then the clock tree, then hold.
• WNS says how far off the worst path is; TNS says how much work is left.

Key words from this volume

Every word below has a plain-English entry in the glossary.

• Timing closure
• Low-Vt cell
• Delay cell
• ECO (engineering change order)
• Spare cells
• Retiming
• WNS (worst negative slack)
• TNS (total negative slack)

Practice

Interview corner

Volume 15 gathers the whole course into one place for revision: a formula sheet, forty numerical problems, twenty concept questions, report-reading drills and flashcards.